Datasheet

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
DS70000318G-page 254  2008-2014 Microchip Technology Inc.
REGISTER 19-6: ADCPC1: ANALOG-TO-DIGITAL CONVERT PAIR
CONTROL REGISTER 1
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IRQEN3
(1)
PEND3
(1)
SWTRG3
(1)
TRGSRC34
(1)
TRGSRC33
(1)
TRGSRC32
(1)
TRGSRC31
(1)
TRGSRC30
(1)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IRQEN2
(2)
PEND2
(2)
SWTRG2
(2)
TRGSRC24
(2)
TRGSRC23
(2)
TRGSRC22
(2)
TRGSRC21
(2)
TRGSRC20
(2)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 IRQEN3: Interrupt Request Enable 3 bit
(1)
1 = Enables IRQ generation when requested conversion of Channels AN7 and AN6 is completed
0 = IRQ is not generated
bit 14 PEND3: Pending Conversion Status 3 bit
(1)
1 = Conversion of Channels AN7 and AN6 is pending; set when selected trigger is asserted
0 = Conversion is complete
bit 13 SWTRG3: Software Trigger 3 bit
(1)
1 = Starts conversion of AN7 and AN6 (if selected by the TRGSRCx bits)
(3)
This bit is automatically cleared by hardware when the PEND3 bit is set.
0 = Conversion has not started
Note 1: These bits are available in the dsPIC33FJ16GS402/404, dsPIC33FJ16GS504, dsPIC33FJ16GS502 and
dsPIC33FJ06GS101 devices only.
2: These bits are available in the dsPIC33FJ16GS502, dsPIC33FJ16GS504, dsPIC33FJ06GS102,
dsPIC33FJ06GS202 and dsPIC33FJ16GS402/404 devices only.
3: The trigger source must be set as a global software trigger prior to setting this bit to ‘1’. If other conversions
are in progress, then the conversion will be performed when the conversion resources are available.