Datasheet

 2008-2014 Microchip Technology Inc. DS70000318G-page 251
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
REGISTER 19-5: ADCPC0: ANALOG-TO-DIGITAL CONVERT PAIR
CONTROL REGISTER 0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IRQEN1 PEND1 SWTRG1
TRGSRC14 TRGSRC13 TRGSRC12 TRGSRC11 TRGSRC10
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IRQEN0 PEND0 SWTRG0
TRGSRC04 TRGSRC03 TRGSRC02 TRGSRC01 TRGSRC00
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 IRQEN1: Interrupt Request Enable 1 bit
1 = Enables IRQ generation when requested conversion of Channels AN3 and AN2 is completed
0 = IRQ is not generated
bit 14 PEND1: Pending Conversion Status 1 bit
1 = Conversion of Channels AN3 and AN2 is pending; set when selected trigger is asserted
0 = Conversion is complete
bit 13 SWTRG1: Software Trigger 1 bit
1 = Starts conversion of AN3 and AN2 (if selected by the TRGSRCx bits)
(1)
This bit is automatically cleared by hardware when the PEND1 bit is set.
0 = Conversion has not started
Note 1: The trigger source must be set as a global software trigger prior to setting this bit to ‘1’. If other conversions
are in progress, then the conversion will be performed when the conversion resources are available.