Datasheet

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
DS70000318G-page 248  2008-2014 Microchip Technology Inc.
bit 4 ASYNCSAMP: Asynchronous Dedicated S&H Sampling Enable bit
(1)
1 = The dedicated S&H is constantly sampling and then terminates sampling as soon as the trigger
pulse is detected
0 = The dedicated S&H starts sampling when the trigger event is detected and completes the sampling
process in two ADC clock cycles
bit 3 Unimplemented: Read as ‘0’
bit 2-0 ADCS<2:0>: Analog-to-Digital Conversion Clock Divider Select bits
(1)
111 = FADC/8
110 = FADC/7
101 = FADC/6
100 = FADC/5
011 = FADC/4 (default)
010 = FADC/3
001 = FADC/2
000 = FADC/1
REGISTER 19-1: ADCON: ANALOG-TO-DIGITAL CONTROL REGISTER (CONTINUED)
Note 1: These control bits can only be changed while ADC is disabled (ADON = 0).
2: These bits are only available on devices with one SAR.