Datasheet

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
DS70000318G-page 240  2008-2014 Microchip Technology Inc.
FIGURE 19-1: ADC BLOCK DIAGRAM FOR dsPIC33FJ06GS101 DEVICES WITH ONE SAR
Even Numbered Inputs with Dedicated
Shared Sample-and-Hold
Data
Format
SAR
Core
Six
Registers
16-Bit
Sample-and-Hold (S&H) Circuits
Bus Interface
AN0
AN1
AN3
AN6
AN7
AN2