Datasheet

 2008-2014 Microchip Technology Inc. DS70000318G-page 229

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

bit 5 ACKDT: Acknowledge Data bit (when operating as I

C master, applicable during master receive)

Value that is transmitted when the software initiates an Acknowledge sequence.

1 = Sends NACK during Acknowledge

0 = Sends ACK during Acknowledge

bit 4 ACKEN: Acknowledge Sequence Enable bit

(when operating as I

C master, applicable during master receive)

1 = Initiates Acknowledge sequence on SDAx and SCLx pins and transmits the ACKDT data bit.

Hardware is clear at end of master Acknowledge sequence.

0 = Acknowledge sequence is not in progress

bit 3 RCEN: Receive Enable bit (when operating as I

C master)

1 = Enables Receive mode for I

C. Hardware is clear at end of eighth bit of master receive data byte.

0 = Receive sequence is not in progress

bit 2 PEN: Stop Condition Enable bit (when operating as I

C master)

1 = Initiates Stop condition on SDAx and SCLx pins. Hardware is clear at end of master Stop sequence.

0 = Stop condition is not in progress

bit 1 RSEN: Repeated Start Condition Enable bit (when operating as I

C master)

1 = Initiates Repeated Start condition on SDAx and SCLx pins. Hardware is clear at end of master

Repeated Start sequence.

0 = Repeated Start condition is not in progress

bit 0 SEN: Start Condition Enable bit (when operating as I

C master)

1 = Initiates Start condition on SDAx and SCLx pins. Hardware is clear at end of master Start

sequence.

0 = Start condition is not in progress