Datasheet

 2008-2014 Microchip Technology Inc. DS70000318G-page 217

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

(1)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PHR PHF PLR PLF FLTLEBEN CLLEBEN LEB6 LEB5

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0

LEB4 LEB3 LEB2 LEB1 LEB0

— — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 PHR: PWMxH Rising Edge Trigger Enable bit

1 = Rising edge of PWMxH will trigger the LEB counter

0 = LEB ignores the rising edge of PWMxH

bit 14 PHF: PWMH Falling Edge Trigger Enable bit

1 = Falling edge of PWMxH will trigger the LEB counter

0 = LEB ignores the falling edge of PWMxH

bit 13 PLR: PWML Rising Edge Trigger Enable bit

1 = Rising edge of PWMxL will trigger the LEB counter

0 = LEB ignores the rising edge of PWMxL

bit 12 PLF: PWML Falling Edge Trigger Enable bit

1 = Falling edge of PWMxL will trigger the LEB counter

0 = LEB ignores the falling edge of PWMxL

bit 11 FLTLEBEN: Fault Input LEB Enable bit

1 = Leading-Edge Blanking is applied to selected Fault input

0 = Leading-Edge Blanking is not applied to selected Fault input

bit 10 CLLEBEN: Current-Limit LEB Enable bit

1 = Leading-Edge Blanking is applied to selected current-limit input

0 = Leading-Edge Blanking is not applied to selected current-limit input

bit 9-3 LEB<6:0>: Leading-Edge Blanking for Current-Limit and Fault Inputs bits

The value is 8.32 nsec increments.

bit 2-0 Unimplemented: Read as ‘0’

Note 1: Configure this register in word format.