Datasheet

 2008-2014 Microchip Technology Inc. DS70000318G-page 161
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
10.7 Peripheral Pin Select Registers
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
families of devices implement 34 registers for
remappable peripheral configuration:
• 15 Input Remappable Peripheral Registers
• 17 Output Remappable Peripheral Registers
Not all output remappable peripheral registers are
implemented on all devices. See the specific register
description for further details.
Note: Input and output register values can only
be changed if OSCCON<IOLOCK> = 0.
See Section 10.6.3.1 “Control Register
Lock” for a specific command sequence.
REGISTER 10-1: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0
U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
— — INT1R5 INT1R4 INT1R3 INT1R2 INT1R1 INT1R0
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’
bit 13-8 INT1R<5:0>: Assign External Interrupt 1 (INTR1) to the Corresponding RPn Pin bits
111111 = Input tied to V
SS
100011 = Input tied to RP35
100010 = Input tied to RP34
100001 = Input tied to RP33
100000 = Input tied to RP32
•
•
•
00000 = Input tied to RP0
bit 7-0 Unimplemented: Read as ‘0’