Datasheet

 2008-2014 Microchip Technology Inc. DS70000318G-page 143
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
REGISTER 8-4: OSCTUN: FRC OSCILLATOR TUNING REGISTER
(1)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — TUN<5:0>
(2)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-6 Unimplemented: Read as ‘0’
bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits
(2)
011111 = Center frequency + 11.6% (8.2268 MHz)
011110 = Center frequency + 11.2% (8.1992 MHz)
•
•
•
000001 = Center frequency + 0.375% (7.3976 MHz)
000000 = Center frequency (7.37 MHz nominal)
111111 = Center frequency – 0.375% (7.2594 MHz)
•
•
•
100001 = Center frequency – 11.6% (6.5132 MHz)
000000 = Center frequency – 12% (6.4856 MHz)
Note 1: This register is reset only on a Power-on Reset (POR).
2: OSCTUN functionality has been provided to help customers compensate for temperature effects on the
FRC frequency over a wide range of temperatures. The tuning step-size is an approximation and is neither
characterized nor tested.