Datasheet

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
DS70000318G-page 124  2008-2014 Microchip Technology Inc.
REGISTER 7-24: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5
REGISTER 7-25: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0
— — — — — INT1IP2 INT1IP1 INT1IP0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-3 Unimplemented: Read as ‘0’
bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0
— INT2IP2 INT2IP1 INT2IP0 — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-7 Unimplemented: Read as ‘0’
bit 6-4 INT2IP<2:0>: External Interrupt 2 Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3-0 Unimplemented: Read as ‘0’