dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 16-Bit Digital Signal Controllers (up to 16-Kbyte Flash and up to 2-Kbyte SRAM) with High-Speed PWM, ADC and Comparators Operating Conditions Advanced Analog Features (Continued) • 3.0V to 3.6V, -40ºC to +150ºC, DC to 20 MIPS • 3.0V to 3.6V, -40ºC to +125ºC, DC to 40 MIPS • 3.0V to 3.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 dsPIC33FJ06GS101/X02 AND dsPIC33FJ16GSX02/X04 PRODUCT FAMILIES The device names, pin counts, memory sizes and peripheral availability of each device are listed below. The following pages show their pinout diagrams.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Pin Diagrams = Pins are up to 5V tolerant 18-Pin SOIC 1 2 AN1/RA1 3 AN2/RA2 4 AN3/RP0(1)/CN0/RB0 5 OSC1/CLKI/AN6/RP1(1)/CN1/RB1 6 OSC2/CLKO/AN7/RP2(1)/CN2/RB2 TCK/PGED2/INT0/RP3(1)/CN3/RB3 7 8 TMS/PGEC2/RP4(1)/CN4/RB4 9 dsPIC33FJ06GS101 MCLR AN0/RA0 18 VDD 17 VSS 16 PWM1L/RA3 15 PWM1H/RA4 14 VCAP 13 VSS PGEC1/SDA1/RP7(1)/CN7/RB7 12 11 PGED1/TDI/SCL1/RP6(1)/CN6/RB6 TDO/RP5(1)/CN5/RB5 10 = Pins are up to 5V tolerant 28-Pin SOIC, SP
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Pin Diagrams (Continued) 28-Pin SPDIP, SOIC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 dsPIC33FJ16GS402 MCLR AN0/RA0 AN1/RA1 AN2/RA2 AN3/RP0(1)/CN0/RB0 AN4/RP9(1)/CN9/RB9 AN5/RP10(1)/CN10/RB10 VSS OSC1/CLKIN/AN6/RP1(1)/CN1/RB1 (1) OSC2/CLKO/AN7/RP2 /CN2/RB2 PGED2/INT0/RP3(1)/CN3/RB3 PGEC2/RP4(1)/CN4/RB4 VDD PGED3/RP8(1)/CN8/RB8 = Pins are up to 5V tolerant 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AVDD AVSS PWM1L/RA3 PWM1H/RA4 PWM2L/RP14(1)/CN14/RB14 PWM2H/RP13(1)/C
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Pin Diagrams (Continued) 28-Pin QFN-S(2) AN1/RA1 AN0/RA0 MCLR AVDD AVSS PWM1L/RA3 PWM1H/RA4 = Pins are up to 5V tolerant 28 27 26 25 24 23 22 1 21 2 20 3 19 4 dsPIC33FJ06GS102 18 5 17 6 16 7 15 8 9 10 11 12 13 14 PWM2L/RP14(1)/CN14/RB14 PWM2H/RP13(1)/CN13/RB13 TCK/RP12(1)/CN12/RB12 TMS/RP11(1)/CN11/RB11 VCAP VSS PGEC1/SDA/RP7(1)/CN7/RB7 28 27 26 25 24 23 22 1 21 2 20 3 19 4 dsPIC33FJ06GS202 18 5 17 6 16 7 15 8 9 10 11 12 13 14 PGED2/DACOUT/INT0/RP3(1)/CN3/RB
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 28-Pin QFN-S(2) 28 27 26 25 24 23 22 1 21 2 20 3 19 4 dsPIC33FJ16GS402 18 5 17 6 16 7 15 8 9 10 11 12 13 14 = Pins are up to 5V tolerant PWM2L/RP14(1)/CN14/RB14 PWM2H/RP13(1)/CN13/RB13 TCK/PWM3L/RP12(1)/CN12/RB12 TMS/PWM3H/RP11(1)/CN11/RB11 VCAP VSS PGEC1/SDA/RP7(1)/CN7/RB7 PGED2/INT0/RP3(1)/CN3/RB3 PGEC2/RP4(1)/CN4/RB4 VDD PGED3/RP8(1)/CN8/RB8 PGEC3/RP15(1)/CN15/RB15 TDO/RP5(1)/CN5/RB5 PGED1/TDI/SCL/RP6(1)/CN6/RB6 AN2/RA2 AN3/RP0(1)/CN0/RB0 AN4/RP9(1)/CN9
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Pin Diagrams (Continued) 44-Pin VTLA(2) PGEC1/SDA/RP7(1)/CN7/RB7 PGED2/INT0/RP3(1)/CN3/RB3 PGEC2/RP4(1)/CN4/RB4 RP18(1)/CN18/RC2 RP23(1)/CN23/RC7 RP24(1)/CN24/RC8 VDD VSS PGED3/RP8(1)/CN8/RB8 PGEC3/RP15(1)/CN15/RB15 TDO/RP5(1)/CN5/RB5 PGED1/TDI/SCL/RP6(1)/CN6/RB6 = Pins are up to 5V tolerant 44 43 42 41 40 39 38 37 36 35 34 33 OSC2/CLKO/AN7/RP2(1)/CN2/RB2 1 32 OSC1/CLKI/AN6/RP1(1)/CN1/RB1 (1) 2 31 RP17(1)/CN17/RC1 (1) RP21 /CN21/RC5 3 3
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Pin Diagrams (Continued) 44-Pin VTLA(2) PGED2/DACOUT/INT0/RP3(1)/CN3/RB3 PGEC2/RP4(1)/CN4/RB4 RP23(1)/CN23/RC7 AN9/EXTREF/CMP4D/RP18(1)/CN18/RC2 VSS RP24(1)/CN24/RC8 VDD PGED3/RP8(1)/CN8/RB8 PGEC3/RP15(1)/CN15/RB15 TDO/RP5(1)/CN5/RB5 PGED1/TDI/SCL/RP6(1)/CN6/RB6 = Pins are up to 5V tolerant 44 43 42 41 40 39 38 37 36 35 34 33 OSC2/CLKO/AN7/CMP3D/CMP4B/RP2(1)/CN2/RB2 PGEC1/SDA/RP7 /CN7/RB7 1 32 OSC1/CLKI/AN6/CMP3C/CMP4A/RP1(1)/CN1/RB1 RP20(1)/C
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Pin Diagrams (Continued) 44-Pin QFN(2) PGED2/INT0/RP3(1)/CN3/RB3 RP18(1)/CN18/RC2 PGEC2/RP4(1)/CN4/RB4 RP23(1)/CN23/RC7 VDD VSS RP24(1)/CN24/RC8 PGED3/RP8(1)/CN8/RB8 PGEC3/RP15(1)/CN15/RB15 PGED1/TDI/SCL/RP6(1)/CN6/RB6 TDO/RP5(1)/CN5/RB5 = Pins are up to 5V tolerant 44 43 42 41 40 39 38 37 36 35 34 PGEC1/SDA/RP7(1)/CN7/RB7 RP20(1)/CN20/RC4 RP21(1)/CN21/RC5 RP22(1)/CN22/RC6 RP19(1)/CN19/RC3 VSS VCAP TMS/PWM3H/RP11(1)/CN11/RB11 TCK/PWM3L/RP12(1)/CN12/RB12
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Pin Diagrams (Continued) 44-Pin QFN(2) PGED2/DACOUT/INT0/RP3(1)/CN3/RB3 RP23(1)/CN23/RC7 AN9/EXTREF/CMP4D/RP18(1)/CN18/RC2 PGEC2/RP4(1)/CN4/RB4 VDD VSS RP24(1)/CN24/RC8 PGEC3/RP15(1)/CN15/RB15 PGED3/RP8(1)/CN8/RB8 PGED1/TDI/SCL/RP6(1)/CN6/RB6 TDO/RP5(1)/CN5/RB5 = Pins are up to 5V tolerant 44 43 42 41 40 39 38 37 36 35 34 PGEC1/SDA/RP7(1)/CN7/RB7 RP20(1)/CN20/RC4 RP21(1)/CN21/RC5 RP22(1)/RN22/RC6 RP19(1)/CN19/RC3 VSS VCAP TMS/PWM3H/RP11(1)/CN11/RB11 TCK
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Pin Diagrams (Continued) 44-Pin TQFP VDD VSS RP24(1)/CN24/RC8 RP23(1)/CN23/RC7 RP18(1)/CN18/RC2 PGEC2/RP4(1)/CN4/RB4 PGED2/INT0/RP3(1)/CN3/RB3 40 39 38 37 36 35 34 42 41 43 PGED1/TDI/SCL/RP6(1)/CN6/RB6 TDO/RP5(1)/CN5/RB5 PGEC3/RP15(1)/CN15/RB15 PGED3/RP8(1)/CN8/RB8 26 AN5/RP10(1)/CN10/RB10 AN4/RP9(1)/CN9/RB9 AN3/RP0(1)/CN0/RB0 AN2/RA2 AN0/RA0 AN1/RA1 RP28 /CN28/RC12 25 24 23 OSC2/CLKO/AN7/RP2(1)/CN2/RB2 OSC1/CLKI/AN6/RP1(1)/CN1/RB1 RP17(1)/CN17/R
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Pin Diagrams (Continued) 44-Pin TQFP VDD VSS RP24(1)/CN24/RC8 RP23(1)/CN23/RC7 AN9/EXTREF/CMP4D/RP18(1)/CN18/RC2 PGEC2/RP4(1)/CN4/RB4 PGED2/DACOUT/INT0/RP3(1)/CN3/RB3 40 39 38 37 36 35 34 42 41 PGED1/TDI/SCL/RP6(1)/CN6/RB6 TDO/RP5(1)/CN5/RB5 PGEC3/RP15(1)/CN15/RB15 PGED3/RP8(1)/CN8/RB8 43 44 33 32 31 30 29 28 27 dsPIC33FJ16GS504 25 24 23 OSC2/CLKO/AN7/CMP3D/CMP4B/RP2(1)/CN2/RB2 OSC1/CLKI/AN6/CMP3C/CMP4A/RP1(1)/CN1/RB1 AN8/CMP4C/RP17(1)/CN17/RC1 VSS
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Table of Contents dsPIC33FJ06GS101/X02 AND dsPIC33FJ16GSX02/X04 Product Families......................................................................................... 2 1.0 Device Overview ........................................................................................................................................................................ 17 2.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers ............................
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Referenced Sources This device data sheet is based on the following individual chapters of the “dsPIC33/PIC24 Family Reference Manual”. These documents should be considered as the primary reference for the operation of a particular module or device feature. Note: To access the documents listed below, browse to the documentation section of the dsPIC33FJ16GS504 product page of the Microchip web site (www.microchip.com).
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70000318G-page 16 2008-2014 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 1.0 DEVICE OVERVIEW Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip web site (www.microchip.com) for the latest “dsPIC33F/PIC24H Family Reference Manual” sections.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 1-1: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 BLOCK DIAGRAM PSV & Table Data Access Control Block Y Data Bus X Data Bus Interrupt Controller 16 8 PORTA 16 16 16 Data Latch Data Latch X RAM Y RAM Address Latch Address Latch 23 23 PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic PORTB 16 23 16 16 PORTC Address Generator Units Address Latch Program Memory EA MUX Data Latch ROM Latch 24 Instruction Reg Control
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 1-1: Pin Name PINOUT I/O DESCRIPTIONS Pin Type Buffer Type PPS Capable Description AN0-AN11 I Analog No Analog input channels CLKI I ST/CMOS No CLKO O — No External clock source input. Always associated with OSC1 pin function. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 1-1: Pin Name PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Type Buffer Type PPS Capable I I I I I I I I I I I I I I I I Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog No No No No No No No No No No No No No No No No CMP1A CMP1B CMP1C CMP1D CMP2A CMP2B CMP2C CMP2D CMP3A CMP3B CMP3C CMP3D CMP4A CMP4B CMP4C CMP4D Description Comparator 1 Channel A. Comparator 1 Channel B.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 2.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT DIGITAL SIGNAL CONTROLLERS Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION 0.1 µF Ceramic 10 µF Tantalum R1 VDD R VSS 2.4 VCAP VDD dsPIC33F VSS VDD VSS VDD AVSS VDD AVDD VSS 0.1 µF Ceramic 0.1 µF Ceramic 0.1 µF Ceramic L1(1) 1: As an option, instead of a hard-wired connection, an inductor (L1) can be substituted between VDD and AVDD to improve ADC noise rejection. The inductor impedance should be less than 1 and the inductor capacity greater than 10 mA.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 2.5 ICSP™ Pins FIGURE 2-3: The PGECx and PGEDx pins are used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 2.8 Configuration of Analog and Digital Pins During ICSP Operations If MPLAB ICD 2, ICD 3 or REAL ICE is selected as a debugger, it automatically initializes all of the A/D input pins (ANx) as “digital” pins, by setting all bits in the ADPCFG register.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 2-4: DIGITAL PFC IPFC VHV_BUS |VAC| k1 k3 VAC FET Driver k2 ADC Channel ADC Channel PWM Output ADC Channel dsPIC33FJ06GS101 FIGURE 2-5: BOOST CONVERTER IMPLEMENTATION IPFC VINPUT VOUTPUT k1 k3 ADC Channel k2 FET Driver ADC Channel PWM Output ADC Channel dsPIC33FJ06GS101 2008-2014 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 2-6: SINGLE-PHASE SYNCHRONOUS BUCK CONVERTER 12V Input 5V Output k7 FET Driver k1 k2 ADC Channel PWM PWM I5V Analog Comp. ADC Channel dsPIC33FJ06GS202 FIGURE 2-7: MULTI-PHASE SYNCHRONOUS BUCK CONVERTER 3.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 2-8: OFF-LINE UPS VDC Push-Pull Converter Full-Bridge Inverter VOUT+ VBAT + VOUTGND GND FET Driver FET Driver PWM PWM k2 k1 ADC ADC or Analog Comp. k3 FET Driver FET Driver FET Driver FET Driver PWM PWM PWM PWM k4 k5 ADC dsPIC33FJ16GS504 ADC ADC ADC PWM FET Driver k6 + Battery Charger 2008-2014 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 2-9: INTERLEAVED PFC VOUT+ |VAC| k4 VAC k3 k1 k2 VOUTFET Driver ADC Channel ADC Channel DS70000318G-page 28 PWM FET Driver ADC Channel PWM ADC Channel ADC Channel dsPIC33FJ06GS202 2008-2014 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 2-10: PHASE-SHIFTED FULL-BRIDGE CONVERTER VIN+ Gate 6 Gate 3 Gate 1 VOUT+ S1 S3 VOUT- Gate 2 Gate 4 Gate 5 Gate 6 Gate 5 VIN- FET Driver k2 PWM ADC Channel k1 Analog Ground Gate 1 S1 FET Driver PWM Gate 3 S3 FET Driver ADC Channel dsPIC33FJ06GS202 PWM Gate 2 Gate 4 2008-2014 Microchip Technology Inc.
AC-TO-DC POWER SUPPLY WITH PFC AND THREE OUTPUTS (12V, 5V AND 3.3V) ZVT with Current Doubler Synchronous Rectifier VHV_BUS Isolation Barrier VOUT IZVT 3.3V Multi-Phase Buck Stage 3.3V Output 12V Input I3.3V_1 FET Driver FET Driver k4 FET Driver 5V Output 5V Buck Stage I3.3V_2 ADC ADC Channel Channel FET Driver ADC Ch. ADC Ch. PWM Output PWM ADC Ch. k5 FET Driver k6 k7 ADC Channel Analog Comp.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 3.0 CPU Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “CPU” (DS70204) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 3.3 Special MCU Features The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 devices support 16/16 and 32/16 divide operations, both fractional and integer. All divide instructions are iterative operations. They must be executed within a REPEAT loop, resulting in a total execution time of 19 instruction cycles. The divide operation can be interrupted during any of those 19 cycles without loss of data.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 3-2: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 PROGRAMMER’S MODEL D15 D0 W0/WREG PUSH.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 3.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 3-1: SR: CPU STATUS REGISTER (CONTINUED) bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2,3) 111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 3-2: CORCON: CORE CONTROL REGISTER U-0 U-0 U-0 R/W-0 R/W-0 R-0 R-0 R-0 — — — US EDT(1) DL2 DL1 DL0 bit 15 bit 8 R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0 SATA SATB SATDW ACCSAT IPL3(2) PSV RND IF bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit -n = Value at POR 0’ = Bit is cleared ‘x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set bit 15-13 Unimplemented:
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 3-2: CORCON: CORE CONTROL REGISTER (CONTINUED) bit 1 RND: Rounding Mode Select bit 1 = Biased (conventional) rounding is enabled 0 = Unbiased (convergent) rounding is enabled bit 0 IF: Integer or Fractional Multiplier Mode Select bit 1 = Integer mode is enabled for DSP multiply ops 0 = Fractional mode is enabled for DSP multiply ops Note 1: 2: This bit will always read as ‘0’.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 3.5 Arithmetic Logic Unit (ALU) The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are 2’s complement in nature. Depending on the operation, the ALU can affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 3-3: DSP ENGINE BLOCK DIAGRAM 40 S a 40 Round t 16 u Logic r a t e 40-Bit Accumulator A 40-Bit Accumulator B Carry/Borrow Out Saturate Adder Carry/Borrow In Negate 40 40 40 16 X Data Bus Barrel Shifter 40 Y Data Bus Sign-Extend 32 16 Zero Backfill 32 33 17-Bit Multiplier/Scaler 16 16 To/From W Array 2008-2014 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 3.6.1 MULTIPLIER The 17-bit x 17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a scaler to support either 1.31 fractional (Q31) or 32-bit integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed operands are sign-extended into the 17th bit of the multiplier input value.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 The SA and SB bits are modified each time data passes through the adder/subtracter, but can only be cleared by the user application. When set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit saturation or bit 39 for 40-bit saturation) and will be saturated (if saturation is enabled). When saturation is not enabled, SA and SB default to bit 39 overflow and thus, indicate that a catastrophic overflow has occurred.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 The SAC and SAC.R instructions store either a truncated (SAC), or rounded (SAC.R) version of the contents of the target accumulator to data memory via the X bus, subject to data saturation (see Section 3.6.3.2 “Data Space Write Saturation”). For the MAC class of instructions, the accumulator writeback operation functions in the same manner, addressing combined MCU (X and Y) data space though the X bus.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 4.0 MEMORY ORGANIZATION Note: This data sheet summarizes the features of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “Program Memory” (DS70202) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 4.1.1 PROGRAM MEMORY ORGANIZATION 4.1.2 All dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 devices reserve the addresses between 0x00000 and 0x000200 for hard-coded program execution vectors. A hardware Reset vector is provided to redirect code execution from the default value of the PC on device Reset to the actual start of code. A GOTO instruction is programmed by the user application at 0x000000, with the actual address for the start of code at 0x000002.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 4.2 Data Address Space The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 CPU has a separate, 16-bit-wide data memory space. The data space is accessed using separate Address Generation Units (AGUs) for read and write operations. The data memory maps is shown in Figure 4-3. All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to bytes within the data space.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 4-3: DATA MEMORY MAP FOR dsPIC33FJ06GS101/102 DEVICES WITH 256 BYTES OF RAM MSB Address MSb 2-Kbyte SFR Space 256 Bytes SRAM Space LSb 0x0000 0x0001 SFR Space 0x07FF 0x0801 0x087F 0x0881 0x07FE 0x0800 X Data RAM (X) Y Data RAM (Y) 0x087E 0x0880 0x08FF 0x0901 0x08FE 0x0900 0x1FFF 0x2001 0x1FFE 0x8001 0x8000 8-Kbyte Near Data Space 0x2000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFF DS70000318G-page 46 LSB Addres
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 4-4: DATA MEMORY MAP FOR dsPIC33FJ06GS202 DEVICE WITH 1-KBYTE RAM MSB Address MSb 2-Kbyte SFR Space 1-Kbyte SRAM Space LSB Address 16 Bits LSb 0x0000 0x0001 SFR Space 0x07FF 0x0801 0x09FF 0x0A01 0x07FE 0x0800 X Data RAM (X) Y Data RAM (Y) 0x09FE 0x0A00 0x0BFF 0x0C01 0x0BFE 0x0C00 0x1FFF 0x2001 0x1FFE 0x8001 0x8000 8-Kbyte Near Data Space 0x2000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFF 2008-2014 Microchip
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 4-5: DATA MEMORY MAP FOR dsPIC33FJ16GS402/404/502/504 DEVICES WITH 2-KBYTE RAM MSB Address MSb 2-Kbyte SFR Space 2-Kbyte SRAM Space LSb 0x0000 0x0001 SFR Space 0x07FF 0x0801 0x07FE 0x0800 X Data RAM (X) 0x0BFF 0x0C01 0x0BFE 0x0C00 Y Data RAM (Y) 0x0FFF 0x1001 0x0FFE 0x1000 0x1FFF 0x2001 0x1FFE 0x8001 0x8000 8-Kbyte Near Data Space 0x2000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFF DS70000318G-page 48 LSB Addr
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 4.2.5 X AND Y DATA SPACES The core has two data spaces, X and Y. These data spaces can be considered either separate (for some DSP instructions), or as one unified linear address range (for MCU instructions). The data spaces are accessed using two Address Generation Units (AGUs) and separate data paths.
File Name SFR Addr CPU CORE REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets WREG0 0000 Working Register 0 0000 WREG1 0002 Working Register 1 0000 WREG2 0004 Working Register 2 0000 WREG3 0006 Working Register 3 0000 WREG4 0008 Working Register 4 0000 WREG5 000A Working Register 5 0000 WREG6 000C Working Register 6 0000 WREG7 000E Working Register 7 0000 WREG8 0010 Working Regist
CPU CORE REGISTER MAP (CONTINUED) SFR Addr File Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets XMODSRT 0048 XS<15:1> 0 xxxx XMODEND 004A XE<15:1> 1 xxxx YMODSRT 004C YS<15:1> 0 xxxx YMODEND 004E YE<15:1> 1 xxxx XBREV 0050 BREN XB14 XB0 xxxx DISICNT 0052 — — Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
File Name SFR Addr INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ06GS101 DEVICES ONLY Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 INTCON1 0080 NSTDIS OVAERR INTCON2 0082 ALTIVT DISI — — — OVBERR COVAERR COVBERR Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 OVATE OVBTE COVTE — — — — — — — — SFTACERR DIV0ERR Bit 5 — Bit 4 Bit 3 MATHERR ADDRERR Bit 0 All Resets OSCFAIL — 0000 INT1EP INT0EP 0000 Bit 2 Bit 1 STKERR INT2EP 2008-2014 Microchip Technology Inc.
File Name SFR Addr INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ06GS102 DEVICES ONLY Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 INTCON1 0080 NSTDIS OVAERR INTCON2 0082 ALTIVT DISI — — — OVBERR COVAERR COVBERR Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 OVATE OVBTE COVTE — — — — — — — — SFTACERR DIV0ERR Bit 5 — Bit 4 Bit 3 MATHERR ADDRERR Bit 0 All Resets OSCFAIL — 0000 INT1EP INT0EP 0000 Bit 2 Bit 1 STKERR INT2EP DS70000318G-page 53 IFS0 0084 — — ADIF U1TXIF U1RXIF SPI1
File Name SFR Addr INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ06G202 DEVICES ONLY Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 INTCON1 0080 NSTDIS OVAERR INTCON2 0082 ALTIVT DISI — — — OVBERR COVAERR COVBERR Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 OVATE OVBTE COVTE — — — — — — — — INT2EP SFTACERR DIV0ERR Bit 5 — Bit 4 Bit 3 Bit 2 MATHERR ADDRERR STKERR Bit 0 All Resets OSCFAIL — 0000 INT1EP INT0EP 0000 Bit 1 2008-2014 Microchip Technology Inc.
File Name SFR Addr INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ16GS402/404 DEVICES ONLY Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 INTCON1 0080 NSTDIS OVAERR INTCON2 0082 ALTIVT DISI — — — OVBERR COVAERR COVBERR Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 OVATE OVBTE COVTE — — — — — — — — INT2EP SFTACERR DIV0ERR Bit 5 — Bit 4 Bit 3 Bit 2 MATHERR ADDRERR STKERR Bit 0 All Resets OSCFAIL — 0000 INT1EP INT0EP 0000 Bit 1 DS70000318G-page 55 IFS0 0084 — — ADIF U1TXIF U1RXIF
File Name SFR Addr INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ16GS502 DEVICES ONLY Bit 15 INTCON1 0080 NSTDIS INTCON2 0082 Bit 14 OVAERR Bit 13 Bit 12 Bit 11 OVBERR COVAERR COVBERR Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 SFTACERR DIV0ERR Bit 5 — Bit 4 Bit 3 Bit 2 MATHERR ADDRERR STKERR Bit 1 Bit 0 All Resets OVATE OVBTE COVTE OSCFAIL — 0000 ALTIVT DISI — — — — — — — — — — — INT2EP INT1EP INT0EP 0000 2008-2014 Microchip Technology Inc.
File Name SFR Addr INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ16GS504 DEVICES ONLY Bit 15 INTCON1 0080 NSTDIS INTCON2 0082 Bit 14 OVAERR Bit 13 Bit 12 Bit 11 OVBERR COVAERR COVBERR Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 SFTACERR DIV0ERR Bit 5 — Bit 4 Bit 3 Bit 2 MATHERR ADDRERR STKERR Bit 1 Bit 0 All Resets OVATE OVBTE COVTE OSCFAIL — 0000 ALTIVT DISI — — — — — — — — — — — INT2EP INT1EP INT0EP 0000 DS70000318G-page 57 IFS0 0084 — — ADIF U1TXIF U1RXIF SPI1IF
File Name SFR Addr TIMER REGISTER MAP FOR dsPIC33FJ06GS101 AND dsPIC33FJ06GSX02 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 TMR1 0100 Timer1 Register PR1 0102 Period Register 1 T1CON 0104 TON — TSIDL — — — — — — TMR2 0106 Timer2 Register PR2 010C Period Register 2 T2CON 0110 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
File Name INPUT CAPTURE REGISTER MAP FOR dsPIC33FJ16GSX02 AND dsPIC33FJ16GSX04 SFR Addr IC1BUF 0140 IC1CON 0142 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 — — ICSIDL — — — — — — ICSIDL — — — — Bit 8 Bit 7 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000 ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 Input Capture 1 Register — ICTMR IC2BUF 0144 IC2CON 0146 Legend: x = unknown value on Reset, — = unimplemented, read as
File Name SFR Addr HIGH-SPEED PWM GENERATOR 1 REGISTER MAP Bit 15 PWMCON1 0420 FLTSTAT Bit 13 CLSTAT TRGSTAT Bit 11 Bit 10 FLTIEN CLIEN TRGIEN POLH POLL PMOD1 PMOD0 CLSRC3 CLSRC2 CLSRC1 CLSRC0 Bit 9 Bit 8 Bit 7 Bit 6 ITB MDCS DTC1 DTC0 Bit 5 OVRENH OVRENL OVRDAT1 OVRDAT0 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets — — — CAM XPRES IUE 0000 FLTDAT1 FLTDAT0 CLDAT1 CLDAT0 SWAP OSYNC 0000 FLTSRC2 FLTSRC1 FLTSRC0 FLTPOL FLTMOD1 FLTMOD0 0000 0422 FCLCON1 0424
File Name SFR Addr HIGH-SPEED PWM GENERATOR 3 REGISTER MAP FOR dsPIC33FJ16GSX02/X04 DEVICES ONLY Bit 15 Bit 14 Bit 13 Bit 11 Bit 10 FLTIEN CLIEN TRGIEN POLL PMOD1 PMOD0 CLSRC3 CLSRC2 CLSRC1 CLSRC0 Bit 8 Bit 7 Bit 6 ITB MDCS DTC1 DTC0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0460 FLTSTAT IOCON3 0462 FCLCON3 0464 IFLTMOD CLSRC4 PDC3 0466 PDC3<15:0> 0000 PHASE3 0468 PHASE3<15:0> 0000 DTR3 046C — — DTR3<13:0> 0000 ALTDTR3 046C — — ALTDTR3<13:0> 0000
I2C1 REGISTER MAP File Name SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 I2C1RCV 0200 — — — — — — — — I2C1 Receive Register 0000 I2C1TRN 0202 — — — — — — — — I2C1 Transmit Register 00FF I2C1BRG 0204 — — — — — — — I2C1CON 0206 I2CEN — IPMIEN A10M DISSLW SMEN GCEN STREN GCSTAT ADD10 IWCOL I2COV Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Baud Rate Generator Register All Resets 0000 ACKDT ACKEN RCEN PEN RSEN SEN D_A P S
HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ06GS101 DEVICES ONLY File Name SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 ADCON 0300 Bit 7 EIE Bit 6 ADON — ADSIDL SLOWCLK — GSWTRG — FORM ADPCFG 0302 — — — — — — — — ADSTAT 0306 — — — — — — — — ADBASE 0308 ADCPC0 030A IRQEN1 PEND1 SWTRG1 TRGSRC14 TRGSRC13 TRGSRC12 TRGSRC11 TRGSRC10 IRQEN0 PEND0 ADCPC1 030C IRQEN3 PEND3 SWTRG3 TRGSRC34 TRGSRC33 TRGSRC32 TRGSRC31 TRGSRC30 Bit 5 Bit 4 ORDER SE
File Name HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ06GS202 DEVICES ONLY SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 ADCON 0300 ADON — ADSIDL SLOWCLK — GSWTRG — FORM EIE ADPCFG 0302 — — — — — — — — — — PCFG5 PCFG4 ADSTAT 0306 — — — — — — — — — P6RDY — — — ADBASE 0308 ADCPC0 030A IRQEN1 PEND1 SWTRG1 TRGSRC14 TRGSRC13 TRGSRC12 TRGSRC11 TRGSRC10 IRQEN0 PEND0 SWTRG0 TRGSRC04 TRGSRC03 TRGSRC02 TRGSRC01 TRGSRC00 0000 ADCPC1 0
File Name HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ16GS502 DEVICES ONLY SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 ADCON 0300 ADON — ADSIDL SLOWCLK — GSWTRG — FORM ADPCFG 0302 — — — — — — — — ADSTAT 0306 — — — — — — — — ADBASE 0308 ADCPC0 030A IRQEN1 PEND1 SWTRG1 TRGSRC14 TRGSRC13 TRGSRC12 TRGSRC11 TRGSRC10 IRQEN0 PEND0 SWTRG0 ADCPC1 030C IRQEN3 PEND3 SWTRG3 TRGSRC34 TRGSRC33 TRGSRC32 TRGSRC31 TRGSRC30 IRQEN2 PEND2 SWTRG2 TRGSRC24 T
File Name SFR Addr HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ16GS504 DEVICES ONLY Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 5 Bit 4 ORDER SEQSAMP ASYNCSAMP Bit 3 Bit 2 Bit 1 Bit 0 All Resets ADCON 0300 ADON — ADSIDL SLOWCLK — GSWTRG — FORM ADPCFG 0302 — — — — PCFG11 PCFG10 PCFG9 PCFG8 ADSTAT 0306 — — — — — — — — ADBASE 0308 ADCPC0 030A IRQEN1 PEND1 SWTRG1 TRGSRC14 TRGSRC13 TRGSRC12 TRGSRC11 TRGSRC10 IRQEN0 PEND0 SWTRG0 TRGSRC04
File Name ANALOG COMPARATOR CONTROL REGISTER MAP FOR dsPIC33FJ06GS202 DEVICES ONLY ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CMPCON1 0540 CMPON — CMPSIDL — — — — DACOE INSEL1 INSEL0 EXTREF — CMPSTAT — CMPPOL RANGE CMPDAC1 0542 — — — — — — CMPCON2 0544 CMPON — CMPSIDL — — — CMPDAC2 0546 — — — — — — TABLE 4-32: File Name CMREF<9:0> — DACOE INSEL1 INSEL0 EXTREF — All Resets 0000 0
PERIPHERAL PIN SELECT INPUT REGISTER MAP File Name SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 RPINR0 0680 — — INT1R5 INT1R4 INT1R3 INT1R2 INT1R1 INT1R0 — — — — — — RPINR1 0682 — — — — — — — — — — INT2R5 INT2R4 INT2R3 INT2R2 RPINR2 0684 — — T1CKR5 T1CKR4 T1CKR3 T1CKR2 T1CKR1 T1CKR0 — — — — — — RPINR3 0686 — — T3CKR5 T3CKR4 T3CKR3 T3CKR2 T3CKR1 T3CKR0 — — T2CKR5 T2CKR4 T2CKR3 RPINR7 068E — — IC2R5
File Name PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ06GS102, dsPIC33FJ06GS202, dsPIC33FJ16GS402 AND dsPIC33FJ16GS502 SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets RPOR0 06D0 — — RP1R5 RP1R4 RP1R3 RP1R2 RP1R1 RP1R0 — — RP0R5 RP0R4 RP0R3 RP0R2 RP0R1 RP0R0 0000 RPOR1 06D2 — — RP3R5 RP3R4 RP3R3 RP3R2 RP3R1 RP3R0 — — RP2R5 RP2R4 RP2R3 RP2R2 RP2R1 RP2R0 0000 RPOR2 06D
File Name PORTA REGISTER MAP SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 TRISA 02C0 — — — — — — — — — — — TRISA<4:0> 001F PORTA 02C2 — — — — — — — — — — — RA<4:0> xxxx LATA 02C4 — — — — — — — — — — — LATA<4:0> ODCA 02C6 — — — — — — — — — — — Legend: Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 ODCA<4:3> — — — 0000 Bit 4 Bit 2 Bit 1 Bit 0 All Resets x = unknown value on Reset, — = unimpleme
File Name SFR Addr SYSTEM CONTROL REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets — — — — CM VREGS EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR xxxx(1) — CLKLOCK IOLOCK LOCK — CF — — RCON 0740 TRAPR IOPUWR OSCCON 0742 — COSC2 COSC1 COSC0 CLKDIV 0744 ROI DOZE2 DOZE1 DOZE0 DOZEN PLLFBD 0746 REFOCON 074E OSCTUN 0748 — — ROON — — — — — ACLKCON 0750 ENAPLL APLLCK SELACLK Le
SFR Name PMD REGISTER MAP FOR dsPIC33FJ06GS202 DEVICES ONLY SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 PMD1 0770 — — — T2MD T1MD — PMD2 0772 — — — — — — PMD3 0774 — — — — — CMPMD PMD4 0776 — — — — — — PMD6 077A — — — — — — PMD7 077C — — — — — — CMP2MD Legend: — — ADCMD 0000 — — OC1MD 0000 — — — — 0000 — REFOMD — — — 0000 — — — — — 0000 — — — — — 0000 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 Bit 4 PW
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 4.2.6 SOFTWARE STACK 4.3 In addition to its use as a Working register, the W15 register in the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices is also used as a software Stack Pointer. The Stack Pointer always points to the first available free word and grows from lower to higher addresses. It predecrements for stack pops and post-increments for stack pushes, as shown in Figure 4-6.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 4-48: FUNDAMENTAL ADDRESSING MODES SUPPORTED Addressing Mode Description File Register Direct The address of the file register is specified explicitly. Register Direct The contents of a register are accessed directly. Register Indirect The contents of Wn forms the Effective Address (EA). Register Indirect Post-Modified The contents of Wn forms the EA. Wn is post-modified (incremented or decremented) by a constant value.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 4.4 Modulo Addressing Note: Modulo Addressing mode is a method used to provide an automated means to support circular data buffers using hardware. The objective is to remove the need for software to perform data address boundary checks when executing tightly looped code, as is typical in many DSP algorithms. Modulo Addressing can operate in either data or program space (since the Data Pointer mechanism is essentially the same for both).
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 4.4.3 MODULO ADDRESSING APPLICABILITY Modulo Addressing can be applied to the Effective Address (EA) calculation associated with any W register.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 4-8: BIT-REVERSED ADDRESS EXAMPLE Sequential Address b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 0 Bit Locations Swapped Left-to-Right Around Center of Binary Value b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1 b2 b3 b4 0 Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-Word Bit-Reversed Buffer TABLE 4-49: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address Bit-Reversed Address A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal 0
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 4.6 4.6.1 Interfacing Program and Data Memory Spaces Since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is needed to create a 23-bit or 24-bit program address from 16-bit data registers. The solution depends on the interface method to be used. The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 architecture uses a 24-bit-wide program space and a 16-bit-wide data space.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 4-9: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Program Counter(1) Program Counter 0 0 23 Bits EA Table Operations(2) 1/0 1/0 TBLPAG 8 Bits 16 Bits 24 Bits Select Program Space Visibility(1) (Remapping) 0 EA 1 0 PSVPAG 8 Bits 15 Bits 23 Bits User/Configuration Space Select Byte Select Note 1: The Least Significant bit (LSb) of program space addresses is always fixed as ‘0’ to maintain word alignment of data in the program and d
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 4.6.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program space without going through data space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data. The PC is incremented by two for each successive 24-bit program word.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 4.6.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This option provides transparent access to stored constant data from the data space without the need to use special instructions (such as TBLRDL/H).
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70000318G-page 82 2008-2014 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 5.0 FLASH PROGRAM MEMORY Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “Flash Programming” (DS70191) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 5.2 RTSP Operation The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user application to erase a page of memory, which consists of eight rows (512 instructions) at a time, and to program one row or one word at a time. Table 24-12 shows typical erase and programming times.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 5-1: NVMCON: FLASH MEMORY CONTROL REGISTER R/SO-0(1) R/W-0(1) R/W-0(1) U-0 U-0 U-0 U-0 U-0 WR WREN WRERR — — — — — bit 15 bit 8 U-0 R/W-0(1) U-0 U-0 R/W-0(1) R/W-0(1) R/W-0(1) R/W-0(1) — ERASE — — NVMOP3(2) NVMOP2(2) NVMOP1(2) NVMOP0(2) bit 7 bit 0 Legend: SO = Settable Only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bi
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 5-2: NVMKEY: NONVOLATILE MEMORY KEY REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 NVMKEY<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 NVMKEY<7:0>: Nonvolatile Memory Key bits (write-only) DS70000318G-page 86 x =
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 5.4.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY 4. 5. One row of program Flash memory can be programmed at a time. To achieve this, it is necessary to erase the 8-row erase page that contains the desired row. The general process is: 1. 2. 3. Read eight rows of program memory (512 instructions) and store in data RAM. Update the program data in RAM with the desired new data.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 EXAMPLE 5-2: LOADING THE WRITE BUFFERS ; Set up NVMCON for row programming operations MOV #0x4001, W0 ; MOV W0, NVMCON ; Initialize NVMCON ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled MOV #0x0000, W0 ; MOV W0, TBLPAG ; Initialize PM Page Boundary SFR MOV #0x6000, W0 ; An example program memory address ; Perform the TBLWT instructions to write the latches ; 0th_program_word MOV #LOW_WORD_0,
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 6.0 RESETS A simplified block diagram of the Reset module is shown in Figure 6-1. Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “Reset” (DS70192) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 RCON: RESET CONTROL REGISTER(1) REGISTER 6-1: R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 TRAPR IOPUWR — — — — CM VREGS bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 EXTR SWR SWDTEN(2) WDTO SLEEP IDLE BOR POR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TRAPR: Trap Reset Flag bit 1 =
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 6-1: RCON: RESET CONTROL REGISTER(1) (CONTINUED) bit 1 BOR: Brown-out Reset Flag bit 1 = A Brown-out Reset has occurred 0 = A Brown-out Reset has not occurred bit 0 POR: Power-on Reset Flag bit 1 = A Power-on Reset has occurred 0 = A Power-on Reset has not occurred Note 1: 2: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 6.1 System Reset • Cold Reset • Warm Reset A Warm Reset is the result of all the other Reset sources, including the RESET instruction. On Warm Reset, the device will continue to operate from the current clock source as indicated by the Current Oscillator Selection (COSC<2:0>) bits in the Oscillator Control (OSCCON<14:12>) register. A Cold Reset is the result of a Power-on Reset (POR) or a Brown-out Reset (BOR).
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 6-2: SYSTEM RESET TIMING VBOR VPOR VDD TPOR 1 POR Reset TBOR 2 BOR Reset 3 TPWRT SYSRST 4 Oscillator Clock TOSCD TOST TLOCK 6 TFSCM FSCM 5 Reset Device Status Run Time Note 1: POR Reset: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is active until VDD crosses the VPOR threshold and the delay, TPOR, has elapsed.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 6.2 Power-on Reset (POR) A Power-on Reset (POR) circuit ensures the device is reset from power-on. The POR circuit is active until VDD crosses the VPOR threshold and the delay, TPOR, has elapsed. The delay, TPOR, ensures the internal device bias circuits become stable. The device supply voltage characteristics must meet the specified starting voltage and rise rate requirements to generate the POR. Refer to Section 24.0 “Electrical Characteristics” for details.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 6.3 External Reset (EXTR) The External Reset is generated by driving the MCLR pin low. The MCLR pin is a Schmitt trigger input with an additional glitch filter. Reset pulses that are longer than the minimum pulse width will generate a Reset. Refer to Section 24.0 “Electrical Characteristics” for minimum pulse width specifications. The External Reset (MCLR) pin (EXTR) bit in the Reset Control (RCON) register is set to indicate the MCLR Reset. 6.3.0.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 6.8.2 UNINITIALIZED W REGISTER RESET The VFC occurs when the Program Counter is reloaded with an interrupt or trap vector. Any attempt to use the Uninitialized W register as an Address Pointer will reset the device. The W register array (with the exception of W15) is cleared during all Resets and is considered uninitialized until written to. 6.8.3 6.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 7.0 INTERRUPT CONTROLLER Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “Interrupts (Part IV)” (DS70300) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available on the Microchip web site (www.microchip.com).
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 7-1: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 INTERRUPT VECTOR TABLE Decreasing Natural Order Priority Reset – GOTO Instruction Reset – GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 ~ ~ ~ Interrupt Vector 52 Interrupt Vector 53 Interrupt Vector 54 ~ ~ ~ Interrupt Vector 116 Interrupt Vector 117 Reserved Rese
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 7-1: INTERRUPT VECTORS Vector Number Interrupt Request (IQR) 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22-23 24 25 26 27 28 29-36 37 38-64 65 66-72 73 74-101 102 103 104 105 106-110 111 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14-15 16 17 18 19 20 21-28 29 30-56 57 58-64 65 66-93 94 95 96 97 98-102 103 112 113 114-117 118 119 120 121 122 123 124 125 104 105 106-109 110 111 112 113 114 115 116 117 IVT Address AIVT Address Interrupt Source Highest Natural Or
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 7.3 Interrupt Control and Status Registers The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 devices implement 27 registers for the interrupt controller: • • • • • • INTCON1 INTCON2 IFSx IECx IPCx INTTREG 7.3.1 INTCON1 AND INTCON2 Global interrupt control functions are controlled from INTCON1 and INTCON2. INTCON1 contains the Interrupt Nesting Disable (NSTDIS) bit as well as the control and status flags for the processor trap sources.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 SR: CPU STATUS REGISTER(1) REGISTER 7-1: R-0 R-0 R/C-0 R/C-0 R-0 R/C-0 R -0 R/W-0 OA OB SA SB OAB SAB DA DC bit 15 bit 8 R/W-0(3) IPL2 R/W-0(3) (2) IPL1 (2) R/W-0(3) IPL0 (2) R-0 R/W-0 R/W-0 R/W-0 R/W-0 RA N OV Z C bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown IPL<2:0>: CPU Interrup
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 SFTACERR DIV0ERR — MATHERR ADDRERR STKERR OSCFAIL — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is un
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED) bit 2 STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ 2008-2014 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-4: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 ALTIVT DISI — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — INT2EP INT1EP INT0EP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit 1 = Use alternate vector
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — ADIF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED) bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS70000318G-page 106 2008-2014 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — INT2IF — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — INT1IF CNIF AC1IF MI2C1IF SI2C1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 INT2IF: External Interrupt
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-7: IFS3: INTERRUPT FLAG STATUS REGISTER 3 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 — — — — — — PSEMIF — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-10 Unimplemented: Read as ‘0’ bit 9 PSEMIF: PWM Special Event Match Interrupt Flag Status bit 1 =
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-9: IFS5: INTERRUPT FLAG STATUS REGISTER 5 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 PWM2IF PWM1IF — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 PWM2IF: PWM2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt reque
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-10: IFS6: INTERRUPT FLAG STATUS REGISTER 6 R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 ADCP1IF ADCP0IF — — — — AC4IF AC3IF bit 15 bit 8 R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 AC2IF — — — — — PWM4IF PWM3IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ADCP1IF: ADC Pair 1 Conversion Done Interrupt Flag Status
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-11: IFS7: INTERRUPT FLAG STATUS REGISTER 7 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — ADCP6IF ADCP5IF ADCP4IF ADCP3IF ADCP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-5 Unimplemented: Read as ‘0’ bit 4 ADCP6IF: ADC Pair 6 Conversio
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-12: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — ADIE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 T2IE OC2IE IC2IE — T1IE OC1IE IC1IE INT0IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-12: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled 2008-2014 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-13: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — INT2IE — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — INT1IE CNIE AC1IE MI2C1IE SI2C1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 INT2IE: External Interr
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-14: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 — — — — — — PSEMIE — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-10 Unimplemented: Read as ‘0’ bit 9 PSEMIE: PWM Special Event Match Interrupt Enable bit 1 = I
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-16: IEC5: INTERRUPT ENABLE CONTROL REGISTER 5 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 PWM2IE PWM1IE — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 PWM2IE: PWM2 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-17: IEC6: INTERRUPT ENABLE CONTROL REGISTER 6 R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 ADCP1IE ADCP0IE — — — — AC4IE AC3IE bit 15 bit 8 R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 AC2IE — — — — — PWM4IE PWM3IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ADCP1IE: ADC Pair 1 Conversion Done Interrupt Enable bi
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-18: IEC7: INTERRUPT ENABLE CONTROL REGISTER 7 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — ADCP6IE ADCP5IE ADCP4IE ADCP3IE ADCP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-5 Unimplemented: Read as ‘0’ bit 4 ADCP6IE: ADC Pair 6 Conver
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-19: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Re
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-20: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T2IP2 T2IP1 T2IP0 — OC2IP2 OC2IP1 OC2IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — IC2IP2 IC2IP1 IC2IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T2
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-21: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — SPI1EIP2 SPI1EIP1 SPI1EIP0 — T3IP2 T3IP1 T3IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplem
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-22: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — ADIP2 ADIP1 ADIP0 — U1TXIP2 U1TXIP1 U1TXIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 ADIP<2:0>: ADC1 Conv
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-23: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — CNIP2 CNIP1 CNIP0 — AC1IP2 AC1IP1 AC1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — MI2C1IP2 MI2C1IP1 MI2C1IP0 — SI2C1IP2 SI2C1IP1 SI2C1IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplem
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-24: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — INT1IP2 INT1IP1 INT1IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Prio
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-26: IPC14: INTERRUPT PRIORITY CONTROL REGISTER 14 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — PSEMIP2 PSEMIP1 PSEMIP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 PSEMIP<2:0>: PWM
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-28: IPC23: INTERRUPT PRIORITY CONTROL REGISTER 23 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — PWM2IP2 PWM2IP1 PWM2IP0 — PWM1IP2 PWM1IP1 PWM1IP0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 PWM2IP<2:0>:
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-29: IPC24: INTERRUPT PRIORITY CONTROL REGISTER 24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — PWM4IP2 PWM4IP1 PWM4IP0 — PWM3IP2 PWM3IP1 PWM3IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 PWM4IP<2:0>:
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-30: IPC25: INTERRUPT PRIORITY CONTROL REGISTER 25 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — AC2IP2 AC2IP1 AC2IP0 — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 AC2IP<2:0>: Analog Comparator 2 Interru
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-31: IPC26: INTERRUPT PRIORITY CONTROL REGISTER 26 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — AC4IP2 AC4IP1 AC4IP0 — AC3IP2 AC3IP1 AC3IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 AC4IP<2:0>: Analog
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-32: IPC27: INTERRUPT PRIORITY CONTROL REGISTER 27 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — ADCP1IP2 ADCP1IP1 ADCP1IP0 — ADCP0IP2 ADCP0IP1 ADCP0IP0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-33: IPC28: INTERRUPT PRIORITY CONTROL REGISTER 28 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — ADCP5IP2 ADCP5IP1 ADCP5IP0 — ADCP4IP2 ADCP4IP1 ADCP4IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — ADCP3IP2 ADCP3IP1 ADCP3IP0 — ADCP2IP2 ADCP2IP1 ADCP2IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-34: IPC29: INTERRUPT PRIORITY CONTROL REGISTER 29 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — ADCP6IP2 ADCP6IP1 ADCP6IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 ADCP6IP<2:0>:
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-35: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 — — — — ILR3 ILR2 ILR1 ILR0 bit 15 bit 8 U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 ILR
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 7.4 7.4.3 Interrupt Setup Procedures 7.4.1 INITIALIZATION Complete the following steps to configure an interrupt source at initialization: 1. 2. Set the NSTDIS bit (INTCON1<15>) if nested interrupts are not desired. Select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate IPCx register. The priority level will depend on the specific application and type of interrupt source.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 8.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 8.1 CPU Clocking System The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 devices provide six system clock options: • • • • • • Fast RC (FRC) Oscillator FRC Oscillator with PLL Primary (XT, HS or EC) Oscillator Primary Oscillator with PLL Low-Power RC (LPRC) Oscillator FRC Oscillator with Postscaler 8.1.1 The FRC frequency depends on the FRC accuracy (see Table 24-20) and the value of the FRC Oscillator Tuning register (see Register 8-4). 8.1.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 8.1.3 PLL CONFIGURATION The primary oscillator and internal FRC oscillator can optionally use an on-chip PLL to obtain higher speeds of operation. The PLL provides significant flexibility in selecting the device operating speed. A block diagram of the PLL is shown in Figure 8-2. The output of the primary oscillator or FRC, denoted as ‘FIN’, is divided down by a prescale factor (N1) of 2, 3, ...
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 8.2 Auxiliary Clock Generation The auxiliary clock generation is used for a peripherals that need to operate at a frequency unrelated to the system clock such as a PWM or ADC. The primary oscillator and internal FRC oscillator sources can be used with an auxiliary PLL to obtain the auxiliary clock. The auxiliary PLL has a fixed 16x multiplication factor. 8.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 8.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER(1,2) (CONTINUED) bit 3 CF: Clock Fail Detect bit (read/clear by application) 1 = FSCM has detected clock failure 0 = FSCM has not detected clock failure bit 2-1 Unimplemented: Read as ‘0’ bit 0 OSWEN: Oscillator Switch Enable bit 1 = Request oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switch is complete Note 1: 2: 3: Writes to this register require an unlock sequence.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 8-2: CLKDIV: CLOCK DIVISOR REGISTER(1) R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 ROI DOZE2 DOZE1 DOZE0 DOZEN(2) FRCDIV2 FRCDIV1 FRCDIV0 bit 15 bit 8 R/W-0 R/W-1 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PLLPOST1 PLLPOST0 — PLLPRE4 PLLPRE3 PLLPRE2 PLLPRE1 PLLPRE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 PLLFBD: PLL FEEDBACK DIVISOR REGISTER(1) REGISTER 8-3: U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — PLLDIV<8> bit 15 bit 8 R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 PLLDIV<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8-0 PLLDIV<8:0>: PLL Feedback Divisor
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 8-4: OSCTUN: FRC OSCILLATOR TUNING REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TUN<5:0>(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits(2) 011111 = Center fr
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 ACLKCON: AUXILIARY CLOCK DIVISOR CONTROL REGISTER(1) REGISTER 8-5: R/W-0 R-0 R/W-1 U-0 U-0 R/W-1 ENAPLL APLLCK SELACLK — — APSTSCLR2 R/W-1 R/W-1 APSTSCLR1 APSTSCLR0 bit 15 bit 0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 ASRCSEL FRCSEL — — — — — — bit 7 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ENAPLL: Auxiliary
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 8-6: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ROON — ROSSLP ROSEL RODIV3(1) RODIV2(1) RODIV1(1) RODIV0(1) bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — bit 7 U-0 — bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ROON: Reference Oscillator Output Enable bi
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 8.5 Clock Switching Operation Users can switch applications among any of the four clock sources (primary, LP, FRC and LPRC) under software control at any time. To limit the possible side effects of this flexibility, dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices have a safeguard lock built into the switch process. Note: 8.5.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 9.0 POWER-SAVING FEATURES Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “Watchdog Timer and Power-Saving Modes” (DS70196) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 9.2.2 IDLE MODE The following occur in Idle mode: • The CPU stops executing instructions • The WDT is automatically cleared • The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 9.4 “Peripheral Module Disable”).
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 9-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 — — T3MD T2MD T1MD — PWMMD(1) — bit 15 bit 8 R/W-0 U-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 I2C1MD — U1MD — SPI1MD — — ADCMD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 T3MD: T
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 9-2: PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — IC2MD IC1MD bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — OC2MD OC1MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-10 Unimplemented: Read as ‘0’ bit 9 IC2MD: Input Capture 2 Module Dis
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 9-3: PMD3: PERIPHERAL MODULE DISABLE CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 U-0 — — — — — CMPMD — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10 CMPMD: Analog Comparator Module Disable bit 1 = An
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 9-5: PMD6: PERIPHERAL MODULE DISABLE CONTROL REGISTER 6 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — PWM4MD PWM3MD PWM2MD PWM1MD bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 Unimplemented: Read as ‘0’ bit 11 PWM4MD: PWM Generator 4 Modu
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 9-6: PMD7: PERIPHERAL MODULE DISABLE CONTROL REGISTER 7 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — CMP4MD CMP3MD CMP2MD CMP1MD bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 Unimplemented: Read as ‘0’ bit 11 CMP4MD: Analog Comparator 4
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70000318G-page 154 2008-2014 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 10.0 I/O PORTS Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “I/O Ports” (DS70193) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available on Microchip web site (www.microchip.com).
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 10.2 Open-Drain Configuration In addition to the PORTx, LATx and TRISx registers for data control, some digital-only port pins can also be individually configured for either digital or open-drain output. This is controlled by the Open-Drain Control register, ODCx, associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain output.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 10.6 Peripheral Pin Select Peripheral Pin Select configuration enables peripheral set selection and placement on a wide range of I/O pins. By increasing the pinout options available on a particular device, programmers can better tailor the microcontroller to their entire application, rather than trimming the application to fit the device. The Peripheral Pin Select configuration feature operates over a fixed subset of digital I/O pins.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 10-1: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION) Function Name Register Configuration Bits INT1 RPINR0 INT1R<5:0> External Interrupt 2 INT2 RPINR1 INT2R<5:0> Timer1 External Clock T1CK RPINR2 T1CKR<5:0> Timer2 External Clock T2CK RPINR3 T2CKR<5:0> Timer3 External Clock Input Name External Interrupt 1 T3CK RPINR3 T3CKR<5:0> Input Capture 1 IC1 RPINR7 IC1R<5:0> Input Capture 2 IC2 RPINR7 IC2R<5:0> Output Compare Fault A
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 10.6.2.2 Output Mapping FIGURE 10-3: In contrast to inputs, the outputs of the Peripheral Pin Select options are mapped on the basis of the pin. In this case, a control register associated with a particular pin dictates the peripheral output to be mapped. The RPORx registers are used to control output mapping.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 10.6.2.3 Virtual Pins dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices support four virtual RPn pins (RP32, RP33, RP34 and RP35), which are identical in functionality to all other RPn pins, with the exception of pinouts. These four pins are internal to the devices and are not connected to a physical device pin. These pins provide a simple way for inter-peripheral connection without utilizing a physical pin.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 10.7 Peripheral Pin Select Registers dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices implement 34 registers for remappable peripheral configuration: Not all output remappable peripheral registers are implemented on all devices. See the specific register description for further details.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-2: RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — INT2R5 INT2R4 INT2R3 INT2R2 INT2R1 INT2R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-3: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — T3CKR5 T3CKR4 T3CKR3 T3CKR2 T3CKR1 T3CKR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — T2CKR5 T2CKR4 T2CKR3 T2CKR2 T2CKR1 T2CKR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bi
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-4: RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — IC2R5 IC2R4 IC2R3 IC2R2 IC2R1 IC2R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — IC1R5 IC1R4 IC1R3 IC1R2 IC1R1 IC1R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Uni
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-5: RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — OCFAR5 OCFAR4 OCFAR3 OCFAR2 OCFAR1 OCFAR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-6: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U1CTSR5 U1CTSR4 U1CTSR3 U1CTSR2 U1CTSR1 U1CTSR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U1RXR5 U1RXR4 U1RXR3 U1RXR2 U1RXR1 U1RXR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unk
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-7: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SCK1R5 SCK1R4 SCK1R3 SCK1R2 SCK1R1 SCK1R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SDI1R5 SDI1R4 SDI1R3 SDI1R2 SDI1R1 SDI1R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-8: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SS1R5 SS1R4 SS1R3 SS1R2 SS1R1 SS1R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 S
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-9: RPINR29: PERIPHERAL PIN SELECT INPUT REGISTER 29 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — FLT1R5 FLT1R4 FLT1R3 FLT1R2 FLT1R1 FLT1R0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-10: RPINR30: PERIPHERAL PIN SELECT INPUT REGISTER 30 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — FLT3R5 FLT3R4 FLT3R3 FLT3R2 FLT3R1 FLT3R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — FLT2R5 FLT2R4 FLT2R3 FLT2R2 FLT2R1 FLT2R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown b
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-11: RPINR31: PERIPHERAL PIN SELECT INPUT REGISTER 31 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — FLT5R5 FLT5R4 FLT5R3 FLT5R2 FLT5R1 FLT5R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — FLT4R5 FLT4R4 FLT4R3 FLT4R2 FLT4R1 FLT4R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown b
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-12: RPINR32: PERIPHERAL PIN SELECT INPUT REGISTER 32 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — FLT7R5 FLT7R4 FLT7R3 FLT7R2 FLT7R1 FLT7R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — FLT6R5 FLT6R4 FLT6R3 FLT6R2 FLT6R1 FLT6R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown b
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-13: RPINR33: PERIPHERAL PIN SELECT INPUT REGISTER 33 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SYNCI1R5 SYNCI1R4 SYNCI1R3 SYNCI1R2 SYNCI1R1 SYNCI1R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — FLT8R5 FLT8R4 FLT8R3 FLT8R2 FLT8R1 FLT8R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit i
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-14: RPINR34: PERIPHERAL PIN SELECT INPUT REGISTER 34 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SYNCI2R5 SYNCI2R4 SYNCI2R3 SYNCI2R2 SYNCI2R1 SYNCI2R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read a
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-16: RPOR1: PERIPHERAL PIN SELECT OUTPUT REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP3R5 RP3R4 RP3R3 RP3R2 RP3R1 RP3R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP2R5 RP2R4 RP2R3 RP2R2 RP2R1 RP2R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unim
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-18: RPOR3: PERIPHERAL PIN SELECT OUTPUT REGISTER 3 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP7R5 RP7R4 RP7R3 RP7R2 RP7R1 RP7R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP6R5 RP6R4 RP6R3 RP6R2 RP6R1 RP6R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unim
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-20: RPOR5: PERIPHERAL PIN SELECT OUTPUT REGISTER 5(1) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP11R5 RP11R4 RP11R3 RP11R2 RP11R1 RP11R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP10R5 RP10R4 RP10R3 RP10R2 RP10R1 RP10R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-22: RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTER 7(1) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP15R5 RP15R4 RP15R3 RP15R2 RP15R1 RP15R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP14R5 RP14R4 RP14R3 RP14R2 RP14R1 RP14R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-24: RPOR9: PERIPHERAL PIN SELECT OUTPUT REGISTER 9(1) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP19R5 RP19R4 RP19R3 RP19R2 RP19R1 RP19R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP18R5 RP18R4 RP18R3 RP18R2 RP18R1 RP18R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-26: RPOR11: PERIPHERAL PIN SELECT OUTPUT REGISTER 11(1) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP23R5 RP23R4 RP23R3 RP23R2 RP23R1 RP23R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP22R5 RP22R4 RP22R3 RP22R2 RP22R1 RP22R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-28: RPOR13: PERIPHERAL PIN SELECT OUTPUT REGISTER 13(1) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP27R5 RP27R4 RP27R3 RP27R2 RP27R1 RP27R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP26R5 RP26R4 RP26R3 RP26R2 RP26R1 RP26R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-30: RPOR16: PERIPHERAL PIN SELECT OUTPUT REGISTER 16 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP33R5 RP33R4 RP33R3 RP33R2 RP33R1 RP33R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP32R5 RP32R4 RP32R3 RP32R2 RP32R1 RP32R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown b
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 11.0 TIMER1 The unique features of Timer1 allow it to be used for Real-Time Clock (RTC) applications. A block diagram of Timer1 is shown in Figure 11-1. Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 11-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 — TGATE TCKPS1 TCKPS0 — TSYNC TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 12.0 TIMER2/3 FEATURES Timer2 is a Type B timer that offers the following major features: Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “Timers” (DS70205) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available on the Microchip web site (www.microchip.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 The Timer2/3 module can operate in one of the following modes: • Timer mode • Gated Timer mode • Synchronous Counter mode In Timer and Gated Timer modes, the input clock is derived from the internal instruction cycle clock (FCY). In Synchronous Counter mode, the input clock is derived from the external clock input at the TxCK pin.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 12-3: 32-BIT TIMER BLOCK DIAGRAM Gate Sync Falling Edge Detect 1 Set TyIF Flag PRy PRx 0 Equal Comparator FCY Prescaler (/n) 10 lsw 00 TCKPS<1:0> Prescaler (/n) TGATE Sync TMRx(1) msw TMRy(2) Reset x1 TxCK TCKPS<1:0> TGATE TMRyHLD TCS Data Bus <15:0> Note 1: 2: Timerx is a Type B Timer (x = 2). Timery is a Type C Timer (y = 3). 2008-2014 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 12-1: TxCON: TIMERx CONTROL REGISTER (x = 2) R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 — TGATE TCKPS1 TCKPS0 T32 — TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timerx On bit When T32 = 1 (in 32-Bit Timer mode): 1 = Starts 3
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 12-2: TyCON: TIMERy CONTROL REGISTER (y = 3) R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON(2) — TSIDL(1) — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 — TGATE(2) TCKPS1(2) TCKPS0(2) — — TCS(2) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timery On bit(2) 1 = Starts 16-bit Timery 0 = Sto
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70000318G-page 190 2008-2014 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 13.0 INPUT CAPTURE Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “Input Capture” (DS70198) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available on the Microchip web site (www.microchip.com).
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 13.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 14.0 OUTPUT COMPARE Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “Output Compare” (DS70005157) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available on the Microchip web site (www.microchip.com).
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 14.1 Output Compare Modes application must disable the associated timer when writing to the Output Compare Control registers to avoid malfunctions. Configure the Output Compare modes by setting the appropriate Output Compare Mode (OCM<2:0>) bits in the Output Compare Control (OCxCON<2:0>) register. Table 14-1 lists the different bit settings for the Output Compare modes. Figure 14-2 illustrates the output compare operation for various modes.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 14-1: OCxCON: OUTPUT COMPARE x CONTROL REGISTER (x = 1, 2) U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — OCSIDL — — — — — bit 15 bit 8 U-0 U-0 U-0 R-0, HC R/W-0 R/W-0 R/W-0 R/W-0 — — — OCFLT OCTSEL OCM2 OCM1 OCM0 bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Un
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70000318G-page 196 2008-2014 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 15.0 HIGH-SPEED PWM Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “High- Speed PWM” (DS70323) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available on the Microchip web site (www.microchip.com).
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 15.2 Feature Description The PWM module is designed for applications that require: • High-resolution at high PWM frequencies • The ability to drive Standard, Edge-Aligned, Center-Aligned Complementary mode, and Push-Pull mode outputs • The ability to create multiphase PWM outputs For Center-Aligned mode, the duty cycle, period phase and dead-time resolutions will be 8.32 ns. Two common, medium power converter topologies are push-pull and half-bridge.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 15-1: SIMPLIFIED CONCEPTUAL BLOCK DIAGRAM OF HIGH-SPEED PWM PWMCONx Pin and Mode Control LEBCONx Control for Blanking External Input Signals TRGCONx ADC Trigger Control Dead-Time Control ALTDTRx, DTRx PWM Enable and Mode Control PTCON MDC Master Duty Cycle Register PDC1 MUX Latch PWM GEN 1 1 Comparator Channel 1 Dead-Time Generator PWM1H Channel 2 Dead-Time Generator PWM2H PWM1L Timer Phase Latch PWM GEN 2 Comparator Timer Phase PDC
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 15-2: PARTITIONED OUTPUT PAIR, COMPLEMENTARY PWM MODE Phase Offset TMR < PDC PWM Dead-Time Timer/Counter Override Logic Logic M U X PWMXH M U X PWMXL Duty Cycle Comparator PWM Duty Cycle Register Channel Override Values Fault Override Values Fault Pin 15.3 Fault Pin Assignment Logic Control Registers The following registers control the operation of the high-speed PWM module.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-1: PTCON: PWM TIME BASE CONTROL REGISTER R/W-0 U-0 R/W-0 HS/HC-0 R/W-0 R/W-0 PTEN — PTSIDL SESTAT SEIEN EIPU(1) R/W-0 R/W-0 SYNCPOL(1) SYNCOEN(1) bit 15 bit 8 R/W-0 U-0 SYNCEN(1) — R/W-0 R/W-0 R/W-0 SYNCSRC1(1) SYNCSRC0(1) SEVTPS3(1) R/W-0 R/W-0 R/W-0 SEVTPS2(1) SEVTPS1(1) SEVTPS0(1) bit 7 bit 0 Legend: HC = Hardware Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bi
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-1: bit 3-0 Note 1: PTCON: PWM TIME BASE CONTROL REGISTER (CONTINUED) SEVTPS<3:0>: PWM Special Event Trigger Output Postscaler Select bits(1) 1111 = 1:16 Postscaler generates a Special Event Trigger trigger on every sixteenth compare match event • • • 0001 = 1:2 Postscaler generates a Special Event Trigger on every second compare match event 0000 = 1:1 Postscaler generates a Special Event Trigger on every compare match event These bits should be ch
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-2: PTCON2: PWM CLOCK DIVIDER SELECT REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — U-0 — — U-0 — U-0 R/W-0 — R/W-0 PCLKDIV<2:0> R/W-0 (1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 PCLKDIV<2:0>: PWM Input Clock P
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-4: R/W-0 SEVTCMP: PWM SPECIAL EVENT COMPARE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SEVTCMP <15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SEVTCMP <7:3> U-0 U-0 U-0 — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-3 SEVTCMP<12:0>: Special Event Compare Count Value bits bit 2-0 Unimplemented: Read
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-6: HS/HC-0 FLTSTAT PWMCONx: PWMx CONTROL REGISTER HS/HC-0 (1) CLSTAT (1) HS/HC-0 TRGSTAT R/W-0 FLTIEN R/W-0 CLIEN R/W-0 R/W-0 TRGIEN ITB (3) R/W-0 MDCS(3) bit 15 bit 8 R/W-0 R/W-0 DTC1 U-0 — DTC0 U-0 — U-0 — R/W-0 CAM (2,3) R/W-0 (4) XPRES R/W-0 IUE bit 7 bit 0 Legend: HC = Hardware Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-6: PWMCONx: PWMx CONTROL REGISTER (CONTINUED) bit 2 CAM: Center-Aligned Mode Enable bit(2,3) 1 = Center-Aligned mode is enabled 0 = Center-Aligned mode is disabled bit 1 XPRES: External PWM Reset Control bit(4) 1 = Current-limit source resets the time base for this PWM generator if it is in Independent Time Base (ITB) mode 0 = External pins do not affect PWM time base bit 0 IUE: Immediate Update Enable bit 1 = Updates to the active MDC/PDCx/SD
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-7: R/W-0 PDCx: PWMx GENERATOR DUTY CYCLE REGISTER(1,2) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PDCx<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PDCx<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 Note 1: 2: x = Bit is unknown PDCx<15:0>: PWM Generator # Duty Cycle Value bits In Independe
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 PHASEx: PWMx PRIMARY PHASE-SHIFT REGISTER(1,2) REGISTER 15-9: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PHASEx<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PHASEx<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 Note 1: 2: x = Bit is unknown PHASEx<15:0>: PWM Phase-Shift Value or Independent Time
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-10: SPHASEx: PWMx SECONDARY PHASE-SHIFT REGISTER(1,2) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SPHASEx<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SPHASEx<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 Note 1: 2: x = Bit is unknown SPHASEx<15:0>: Secondary Phase Offset for PWMxL Ou
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 .
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-13: TRGCONx: PWMx TRIGGER CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0 — — — — bit 15 bit 8 R/W-0 U-0 R/W-0 DTM(1) — TRGSTRT5 R/W-0 R/W-0 TRGSTRT4 TRGSTRT3 R/W-0 R/W-0 R/W-0 TRGSTRT2 TRGSTRT1 TRGSTRT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-14: IOCONx: PWMx I/O CONTROL REGISTER R/W-0 R/W-0 PENH PENL R/W-0 POLH R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 POLL PMOD1(1) PMOD0(1) OVRENH OVRENL bit 15 bit 8 R/W-0 R/W-0 OVRDAT1 OVRDAT0 R/W-0 FLTDAT1 R/W-0 (2) FLTDAT0 R/W-0 (2) (2) CLDAT1 R/W-0 CLDAT0 (2) R/W-0 R/W-0 SWAP OSYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-14: IOCONx: PWMx I/O CONTROL REGISTER (CONTINUED) bit 3-2 CLDAT<1:0>: State for PWMxH and PWMxL Pins if CLMODE is Enabled bits(2) FCLCONx = 0: Normal Fault mode: If current-limit is active, then CLDAT<1> provides the state for PWMxH If current-limit is active, then CLDAT<0> provides the state for PWMxL FCLCONx = 1: Independent Fault mode: CLDAT<1:0> bits are ignored.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-15: FCLCONx: PWMx FAULT CURRENT-LIMIT CONTROL REGISTER R/W-0 R/W-0 IFLTMOD R/W-0 R/W-0 R/W-0 CLSRC4(2,3) CLSRC3(2,3) CLSRC2(2,3) CLSRC1(2,3) R/W-0 R/W-0 R/W-0 CLSRC0(2,3) CLPOL(1) CLMOD bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTSRC4(2,3) FLTSRC3(2,3) FLTSRC2(2,3) FLTSRC1(2,3) FLTSRC0(2,3) R/W-0 R/W-0 R/W-0 FLTPOL(1) FLTMOD1 FLTMOD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-15: FCLCONx: PWMx FAULT CURRENT-LIMIT CONTROL REGISTER (CONTINUED) bit 7-3 FLTSRC<4:0>: Fault Control Signal Source Select for PWM Generator # bits(2,3) 11111 = Reserved • • • 01000 = Reserved 00111 = Fault 8 00110 = Fault 7 00101 = Fault 6 00100 = Fault 5 00011 = Fault 4 00010 = Fault 3 00001 = Fault 2 00000 = Fault 1 bit 2 FLTPOL: Fault Polarity for PWM Generator # bit(1) 1 = The selected Fault source is active-low 0 = The selected Fault source
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-16: TRIGx: PWMx PRIMARY TRIGGER COMPARE VALUE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRGCMP<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRGCMP<7:3> U-0 U-0 U-0 — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 TRGCMP<15:3>: Trigger Control Value bits When primary PWM fu
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-18: LEBCONx: LEADING-EDGE BLANKING CONTROL REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PHR PHF PLR PLF FLTLEBEN CLLEBEN LEB6 LEB5 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 LEB4 LEB3 LEB2 LEB1 LEB0 — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PHR: PW
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-19: PWMCAPx: PRIMARY PWMx TIME BASE CAPTURE REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 PWMCAP<15:8>(1,2) bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 PWMCAP<7:3>(1,2) U-0 U-0 U-0 — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 PWMCAP<15:3>: Captured PWM Time Base Value bits(1,2) The value in this registe
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 16.0 SERIAL PERIPHERAL INTERFACE (SPI) Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “Serial Peripheral Interface (SPI)” (DS70206) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available on the Microchip web site (www.microchip.com).
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 16-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 SPIEN — SPISIDL — — — — — bit 15 bit 8 U-0 R/C-0 U-0 U-0 U-0 U-0 R-0 R-0 — SPIROV — — — — SPITBF SPIRBF bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 SPIEN: SPIx Enable bit 1 = Enab
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 16-2: SPIXCON1: SPIx CONTROL REGISTER 1 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — DISSCK DISSDO MODE16 SMP CKE(1) bit 15 bit 8 R/W-0 R/W-0 (3) CKP SSEN R/W-0 MSTEN R/W-0 (2) SPRE2 R/W-0 (2) SPRE1 R/W-0 SPRE0 (2) R/W-0 PPRE1 (2) R/W-0 PPRE0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 16-2: SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED) bit 4-2 SPRE<2:0>: Secondary Prescale bits (Master mode)(2) 111 = Secondary prescale 1:1 110 = Secondary prescale 2:1 • • • 000 = Secondary prescale 8:1 bit 1-0 PPRE<1:0>: Primary Prescale bits (Master mode)(2) 11 = Primary prescale 1:1 10 = Primary prescale 4:1 01 = Primary prescale 16:1 00 = Primary prescale 64:1 Note 1: 2: 3: The CKE bit is not used in the Framed SPI modes.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 16-3: SPIxCON2: SPIx CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 FRMEN SPIFSD FRMPOL — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 — — — — — — FRMDLY — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FRMEN: Framed SPIx Support bit 1 = Framed SPIx support is enable
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70000318G-page 224 2008-2014 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 17.0 INTER-INTEGRATED CIRCUIT (I2C™) Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “Inter-Integrated Circuit (I2C™)” (DS70000195) in the “dsPIC33/PIC24 Family Reference Manual”, which is available on the Microchip web site (www.microchip.com).
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 17-1: I2Cx BLOCK DIAGRAM (X = 1) Internal Data Bus I2CxRCV Read SCLx Shift Clock I2CxRSR LSb SDAx Address Match Match Detect Write I2CxMSK Write Read I2CxADD Read Start and Stop Bit Detect Write Start and Stop Bit Generation Control Logic I2CxSTAT Collision Detect Read Write I2CxCON Acknowledge Generation Read Clock Stretching Write I2CxTRN LSb Read Shift Clock Reload Control BRG Down Counter Write I2CxBRG Read TCY/2 DS70000318G-pa
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 17.2 I2C Registers I2CxCON and I2CxSTAT are control and status registers. The I2CxCON register is readable and writable. The lower six bits of I2CxSTAT are read-only.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 17-1: I2CxCON: I2Cx CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-1, HC R/W-0 R/W-0 R/W-0 R/W-0 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HC = Hardware Clearable bit -n = Value at POR ‘1’ = Bit is set ‘0’
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 17-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED) bit 5 ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive) Value that is transmitted when the software initiates an Acknowledge sequence.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 17-2: I2CxSTAT: I2Cx STATUS REGISTER R-0, HSC R-0, HSC U-0 U-0 U-0 R/C-0, HSC R-0, HSC R-0, HSC ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 bit 15 bit 8 R/C-0, HS R/C-0, HS R-0, HSC IWCOL I2COV D_A R/C-0, HSC R/C-0, HSC P R-0, HSC R-0, HSC R-0, HSC R_W RBF TBF S bit 7 bit 0 Legend: C = Clearable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 17-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware is set or clear when Start, Repeated Start or Stop is detected. bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware is set or clear when Start, Repeated Start or Stop is detected.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 17-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — R/W-0 R/W-0 AMSK<9:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 AMSK<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9-0 AMSK<9:0>: Mask for Address
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 18.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available on the Microchip web site (www.microchip.com).
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 18-1: R/W-0 UxMODE: UARTx MODE REGISTER U-0 (1) — UARTEN R/W-0 USIDL R/W-0 IREN (2) R/W-0 U-0 R/W-0 R/W-0 RTSMD — UEN1 UEN0 bit 15 bit 8 R/W-0, HC R/W-0 R/W-0, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WAKE LPBACK ABAUD URXINV BRGH PDSEL1 PDSEL0 STSEL bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleare
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 18-1: UxMODE: UARTx MODE REGISTER (CONTINUED) bit 4 URXINV: UARTx Receive Polarity Inversion bit 1 = UxRX Idle state is ‘0’ 0 = UxRX Idle state is ‘1’ bit 3 BRGH: High Baud Rate Enable bit 1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode) 0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode) bit 2-1 PDSEL<1:0>: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 =
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 18-2: R/W-0 UxSTA: UARTx STATUS AND CONTROL REGISTER R/W-0 UTXISEL1 UTXINV R/W-0 UTXISEL0 U-0 R/W-0, HC — UTXBRK R/W-0 (1) UTXEN R-0 R-1 UTXBF TRMT bit 15 bit 8 R/W-0 R/W-0 R/W-0 R-1 R-0 R-0 R/C-0 R-0 URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA bit 7 bit 0 Legend: HC = Hardware Clearable bit C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1) 1 = Address Detect mode is enable; if 9-bit mode is not selected, this does not take effect 0 = Address Detect mode is disabled bit 4 RIDLE: Receiver Idle bit (read-only) 1 = Receiver is Idle 0 = Receiver is active bit 3 PERR: Parity Error Status bit (read-only) 1 = Parity error has been detected for the current charac
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70000318G-page 238 2008-2014 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 19.0 HIGH-SPEED 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “High-Speed 10-Bit Analog-to-Digital Converter (ADC)” (DS70000321) in the “dsPIC33/PIC24 Family Reference Manual”, which is available on the Microchip web site (www.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 19-1: ADC BLOCK DIAGRAM FOR dsPIC33FJ06GS101 DEVICES WITH ONE SAR Even Numbered Inputs with Dedicated Sample-and-Hold (S&H) Circuits AN0 Six 16-Bit Registers Bus Interface SAR Core Data Format AN2 AN1 Shared Sample-and-Hold AN3 AN6 AN7 DS70000318G-page 240 2008-2014 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 19-2: ADC BLOCK DIAGRAM FOR dsPIC33FJ06GS102 DEVICES WITH ONE SAR Even Numbered Inputs with Dedicated Sample-and-Hold (S&H) Circuits AN0 Six 16-Bit Registers Bus Interface SAR Core Data Format AN2 AN1 Shared Sample-and-Hold AN3 AN4 AN5 2008-2014 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 19-3: ADC BLOCK DIAGRAM FOR dsPIC33FJ06GS202 DEVICES WITH ONE SAR Even Numbered Inputs with Dedicated Sample-and-Hold (S&H) Circuits AN0 AN12(1) (EXTREF) Eight 16-Bit Registers Bus Interface SAR Core Data Format AN2 AN1 Shared Sample-and-Hold AN3 AN4 AN5 AN13(2) (INTREF) Note 1: 2: AN12 (EXTREF) is an internal analog input.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 19-4: ADC BLOCK DIAGRAM FOR dsPIC33FJ16GS402/404 DEVICES WITH ONE SAR Even Numbered Inputs with Dedicated Sample-and-Hold (S&H) Circuits AN0 AN2 Eight 16-bit Registers Bus Interface SAR Core Data Format AN4 AN1 AN3 Shared Sample-and-Hold AN5 AN6 AN7 2008-2014 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 19-5: ADC BLOCK DIAGRAM FOR dsPIC33FJ16GS502 DEVICES WITH TWO SARS Even Numbered Inputs with Dedicated Sample-and-Hold (S&H) Circuits AN0 SAR Core Data Format Five 16-Bit Registers SAR Core Data Format AN2 Five 16-Bit Registers AN4 AN6 Bus Interface Even Numbered Inputs with Shared S&H AN12(1) (EXTREF) AN1 Odd Numbered Inputs with Shared S&H AN3 AN5 AN7 AN13(2) (INTREF) Note 1: 2: AN12 (EXTREF) is an internal analog input.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 19-6: ADC BLOCK DIAGRAM FOR dsPIC33FJ16GS504 DEVICES WITH TWO SARS Even Numbered Inputs with Dedicated Sample-and-Hold (S&H) Circuits AN0 Data Format SAR Core Seven 16-Bit Registers Data Format AN2 Seven 16-Bit Registers AN4 AN6 AN8 Bus Interface Even Numbered Inputs with Shared S&H AN10 AN12(1) (EXTREF) AN1 Odd Numbered Inputs with Shared S&H SAR Core AN3 AN5 AN7 AN9 AN11 AN13(2) (INTREF) Note 1: 2: AN12 (EXTREF) is an internal anal
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 19.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-1: ADCON: ANALOG-TO-DIGITAL CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 ADON — ADSIDL SLOWCLK(1) — GSWTRG — FORM(1) bit 15 R/W-0 EIE(1) bit 8 R/W-0 R/W-0 R/W-0 ORDER(1,2) SEQSAMP(1,2) ASYNCSAMP(1) U-0 R/W-0 R/W-1 R/W-1 — ADCS2(1) ADCS1(1) ADCS0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-1: ADCON: ANALOG-TO-DIGITAL CONTROL REGISTER (CONTINUED) bit 4 ASYNCSAMP: Asynchronous Dedicated S&H Sampling Enable bit(1) 1 = The dedicated S&H is constantly sampling and then terminates sampling as soon as the trigger pulse is detected 0 = The dedicated S&H starts sampling when the trigger event is detected and completes the sampling process in two ADC clock cycles bit 3 Unimplemented: Read as ‘0’ bit 2-0 ADCS<2:0>: Analog-to-Digital Conver
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-2: ADSTAT: ANALOG-TO-DIGITAL STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/C-0, HS R/C-0, HS R/C-0, HS R/C-0, HS R/C-0, HS R/C-0, HS R/C-0, HS — P6RDY P5RDY P4RDY P3RDY P2RDY P1RDY P0RDY bit 7 bit 0 Legend: C = Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cl
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 ADBASE: ANALOG-TO-DIGITAL BASE REGISTER(1,2) REGISTER 19-3: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADBASE<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 — ADBASE<7:1> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-1 ADBASE<15:1>: Analog-to-Digital Base bits This register contains the b
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-5: ADCPC0: ANALOG-TO-DIGITAL CONVERT PAIR CONTROL REGISTER 0 R/W-0 R/W-0 R/W-0 IRQEN1 PEND1 SWTRG1 R/W-0 R/W-0 TRGSRC14 TRGSRC13 R/W-0 R/W-0 R/W-0 TRGSRC12 TRGSRC11 TRGSRC10 bit 15 bit 8 R/W-0 R/W-0 R/W-0 IRQEN0 PEND0 SWTRG0 R/W-0 R/W-0 TRGSRC04 TRGSRC03 R/W-0 R/W-0 R/W-0 TRGSRC02 TRGSRC01 TRGSRC00 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = B
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-5: ADCPC0: ANALOG-TO-DIGITAL CONVERT PAIR CONTROL REGISTER 0 (CONTINUED) bit 12-8 TRGSRC1<4:0>: Trigger 1 Source Selection bits Selects trigger source for conversion of Analog Channels AN3 and AN2.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-5: bit 4-0 Note 1: ADCPC0: ANALOG-TO-DIGITAL CONVERT PAIR CONTROL REGISTER 0 (CONTINUED) TRGSRC0<4:0>: Trigger 0 Source Selection bits Selects trigger source for conversion of Analog Channels AN1 and AN0.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-6: ADCPC1: ANALOG-TO-DIGITAL CONVERT PAIR CONTROL REGISTER 1 R/W-0 R/W-0 IRQEN3(1) PEND3(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SWTRG3(1) TRGSRC34(1) TRGSRC33(1) TRGSRC32(1) TRGSRC31(1) TRGSRC30(1) bit 15 bit 8 R/W-0 R/W-0 IRQEN2(2) PEND2(2) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SWTRG2(2) TRGSRC24(2) TRGSRC23(2) TRGSRC22(2) TRGSRC21(2) TRGSRC20(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit,
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-6: ADCPC1: ANALOG-TO-DIGITAL CONVERT PAIR CONTROL REGISTER 1 (CONTINUED) bit 12-8 TRGSRC3<4:0>: Trigger 3 Source Selection bits(1) Selects trigger source for conversion of Analog Channels AN7 and AN6.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-6: ADCPC1: ANALOG-TO-DIGITAL CONVERT PAIR CONTROL REGISTER 1 (CONTINUED) TRGSRC2<4:0>: Trigger 2 Source Selection bits(2) Selects trigger source for conversion of Analog Channels AN5 and AN4.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-7: ADCPC2: ANALOG-TO-DIGITAL CONVERT PAIR CONTROL REGISTER 2(1) R/W-0 R/W-0 R/W-0 IRQEN5 PEND5 SWTRG5 R/W-0 R/W-0 TRGSRC54 TRGSRC53 R/W-0 R/W-0 R/W-0 TRGSRC52 TRGSRC51 TRGSRC50 bit 15 bit 8 R/W-0 R/W-0 R/W-0 IRQEN4 PEND4 SWTRG4 R/W-0 R/W-0 TRGSRC44 TRGSRC43 R/W-0 R/W-0 R/W-0 TRGSRC42 TRGSRC41 TRGSRC40 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-7: ADCPC2: ANALOG-TO-DIGITAL CONVERT PAIR CONTROL REGISTER 2(1) (CONTINUED) bit 12-8 TRGSRC5<4:0>: Trigger 5 Source Selection bits Selects trigger source for conversion of Analog Channels AN11 and AN10.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-7: bit 4-0 Note 1: 2: ADCPC2: ANALOG-TO-DIGITAL CONVERT PAIR CONTROL REGISTER 2(1) (CONTINUED) TRGSRC4<4:0>: Trigger 4 Source Selection bits Selects trigger source for conversion of Analog Channels AN9 and AN8.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 ADCPC3: ANALOG-TO-DIGITAL CONVERT PAIR CONTROL REGISTER 3(1) REGISTER 19-8: U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 IRQEN6 PEND6 SWTRG6 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRGSRC6<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-8: bit 4-0 Note 1: 2: ADCPC3: ANALOG-TO-DIGITAL CONVERT PAIR CONTROL REGISTER 3(1) TRGSRC6<4:0>: Trigger 6 Source Selection bits Selects trigger source for conversion of Analog Channels AN13 and AN12.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70000318G-page 262 2008-2014 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 20.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 20.3 Module Applications 20.5 Interaction with I/O Buffers This module provides a means for the SMPS dsPIC® DSC devices to monitor voltage and currents in a power conversion application. The ability to detect transient conditions and stimulate the dsPIC DSC processor and/or peripherals, without requiring the processor and ADC to constantly monitor voltages or currents, frees the dsPIC DSC to perform other tasks.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 20-1: CMPCONx: COMPARATOR CONTROL x REGISTER R/W-0 U-0 R/W-0 r-0 r-0 r-0 r-0 R/W-0 CMPON — CMPSIDL r r r r DACOE bit 15 bit 8 R/W-0 R/W-0 R/W-0 r-0 R/W-0 r-0 R/W-0 R/W-0 INSEL1 INSEL0 EXTREF r CMPSTAT r CMPPOL RANGE bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CMPON
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 20-2: CMPDACx: COMPARATOR DAC x CONTROL REGISTER r-0 r-0 r-0 r-0 r-0 r-0 r r r r r r R/W-0 R/W-0 CMREF<9:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CMREF<7:0> bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Reserved: Read as ‘0’ bit 9-0 CMREF<9:0>: Com
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 21.0 SPECIAL FEATURES 21.1 dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices provide nonvolatile memory implementations for device Configuration bits. Refer to “Device Configuration” (DS70194) in the “dsPIC33F/PIC24H Family Reference Manual” for more information on this implementation. Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices. It is not intended to be a comprehensive reference source.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 21-2: Bit Field dsPIC33F CONFIGURATION BITS DESCRIPTION Register RTSP Effect Description BWRP FBS Immediate Boot Segment Program Flash Write Protection bit 1 = Boot segment can be written 0 = Boot segment is write-protected BSS<2:0> FBS Immediate Boot Segment Program Flash Code Protection Size bits x11 = No boot program Flash segment Boot Space is 256 Instruction Words (except interrupt vectors): 110 = Standard security; boot program Flash segme
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 21-2: Bit Field dsPIC33F CONFIGURATION BITS DESCRIPTION (CONTINUED) Register RTSP Effect POSCMD<1:0> FOSC Immediate Primary Oscillator Mode Select bits 11 = Primary Oscillator is disabled 10 = HS Crystal Oscillator mode 01 = XT Crystal Oscillator mode 00 = EC (External Clock) mode FWDTEN FWDT Immediate Watchdog Timer Enable bit 1 = Watchdog Timer is always enabled (LPRC oscillator cannot be disabled; clearing the SWDTEN bit in the RCON register w
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 21.2 On-Chip Voltage Regulator 21.3 BOR: Brown-out Reset The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices power their core digital logic at a nominal 2.5V. This can create a conflict for designs that are required to operate at a higher typical voltage, such as 3.3V.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 21.4 21.4.2 Watchdog Timer (WDT) For the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices, the WDT is driven by the LPRC oscillator. When the WDT is enabled, the clock source is also enabled. 21.4.1 PRESCALER/POSTSCALER The nominal WDT clock source from LPRC is 32 kHz. This feeds a prescaler that can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The prescaler is set by the WDTPRE Configuration bit.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 21.5 JTAG Interface 21.7 In-Circuit Debugger The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices implement a JTAG interface, which supports boundary scan device testing. Detailed information on this interface will be provided in future revisions of the document. The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices provide simple debugging functionality through the PGECx (Emulation/Debug Clock) and PGEDx (Emulation/Debug Data) pin functions. 21.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 21.8 Code Protection and CodeGuard™ Security The code protection features are controlled by the Configuration registers: FBS and FGS. The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices offer the intermediate implementation of CodeGuard™ Security. CodeGuard Security enables multiple parties to securely share resources (memory, interrupts and peripherals) on a single chip.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70000318G-page 274 2008-2014 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 22.0 Note: INSTRUCTION SET SUMMARY This data sheet summarizes the features of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the latest sections in the “dsPIC33F/PIC24H Family Reference Manual”, which are available on the Microchip web site (www.microchip.com). The dsPIC33F instruction set is identical to that of the dsPIC30F.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Most instructions are a single word. Certain double-word instructions are designed to provide all the required information in these 48 bits. In the second word, the 8 MSbs are ‘0’s. If this second word is executed as an instruction (by itself), it will execute as a NOP. The double-word instructions execute in two instruction cycles.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 22-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED) Field Description Wm*Wm Multiplicand and Multiplier Working register pair for Square instructions {W4 * W4,W5 * W5,W6 * W6,W7 * W7} Wm*Wn Multiplicand and Multiplier Working register pair for DSP instructions {W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7} Wn One of 16 Working registers {W0..W15} Wnd One of 16 Destination Working registers {W0...
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 22-2: Base Instr # 1 2 3 4 5 6 7 8 9 INSTRUCTION SET OVERVIEW Assembly Mnemonic ADD ADDC AND ASR BCLR BRA BSET BSW BTG Assembly Syntax # of # of Words Cycles Description Status Flags Affected ADD Acc Add Accumulators 1 1 ADD f f = f + WREG 1 1 OA,OB,SA,SB C,DC,N,OV,Z ADD f,WREG WREG = f + WREG 1 1 C,DC,N,OV,Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C,DC,N,OV,Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C,DC,N,OV,Z ADD Wb,#
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 22-2: Base Instr # 10 11 12 13 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic BTSC BTSS BTST BTSTS Assembly Syntax Description # of # of Words Cycles Status Flags Affected BTSC f,#bit4 Bit Test f, Skip if Clear 1 1 (2 or 3) None BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1 (2 or 3) None BTSS f,#bit4 Bit Test f, Skip if Set 1 1 (2 or 3) None BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 (2 or 3) None BTST f,#bit4
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 22-2: Base Instr # 29 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic DIV Assembly Syntax # of # of Words Cycles Description Status Flags Affected DIV.S Wm,Wn Signed 16/16-bit Integer Divide 1 18 N,Z,C,OV DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N,Z,C,OV DIV.U Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N,Z,C,OV DIV.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 22-2: Base Instr # 48 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic MPY Assembly Syntax Description # of # of Words Cycles Status Flags Affected MPY Wm*Wn,Acc,Wx,Wxd,Wy,Wyd Multiply Wm by Wn to Accumulator 1 1 OA,OB,OAB, SA,SB,SAB MPY Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square Wm to Accumulator 1 1 OA,OB,OAB, SA,SB,SAB 49 MPY.N MPY.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 22-2: Base Instr # 66 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic RRNC Assembly Syntax # of # of Words Cycles Description Status Flags Affected RRNC f f = Rotate Right (No Carry) f 1 1 N,Z RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N,Z RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N,Z 67 SAC SAC Acc,#Slit4,Wdo Store Accumulator 1 1 None SAC.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 23.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 23.2 MPLAB XC Compilers The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip’s 8, 16 and 32-bit MCU and DSC devices. These compilers provide powerful integration capabilities, superior code optimization and ease of use. MPLAB XC Compilers run on Windows, Linux or MAC OS X. For easy source level debugging, the compilers provide debug information that is optimized to the MPLAB X IDE.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 23.6 MPLAB X SIM Software Simulator The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 23.11 Demonstration/Development Boards, Evaluation Kits and Starter Kits A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 24.0 ELECTRICAL CHARACTERISTICS This section provides an overview of dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 24.1 DC Characteristics TABLE 24-1: OPERATING MIPS VS. VOLTAGE Max MIPS Characteristic VDD Range (in Volts) Temp Range (in °C) — 3.0-3.6V(1) -40°C to +85°C 40 — 3.0-3.6V(1) -40°C to +125°C 40 Note 1: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Overall functional device operation at VBORMIN < VDD < VDDMIN is tested but not characterized. All device analog modules such as the ADC, etc., will function but with degraded performance below VDDMIN.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param Symbol No. Characteristic Min Typ(1) Max Units Conditions Operating Voltage DC10 VDD Supply Voltage(4) 3.0 — 3.6 V DC12 VDR RAM Data Retention Voltage(2) 1.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Parameter Typical(1) No. Max Units Conditions Operating Current (IDD)(2) DC20d 55 70 mA -40°C DC20a 55 70 mA +25°C 10 MIPS 3.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) (CONTINUED) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Parameter Typical(1) No. Max Units Conditions Operating Current (IDD)(2) DC27d 111 140 mA -40°C 40 MIPS DC27a 108 130 mA +25°C See Note 2, except PWM is 3.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Parameter No.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Parameter No.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-8: DC CHARACTERISTICS: DOZE CURRENT (IDOZE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Parameter No.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param Symbol No. VIL Characteristic Min Typ(1) Max Units Conditions Input Low Voltage DI10 I/O Pins VSS — 0.2 VDD V DI15 MCLR VSS — 0.2 VDD V DI16 I/O Pins with OSC1 VSS — 0.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param Symbol No.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param. Symbol DO10 DO20 VOL VOH Characteristic Min. Typ. Max. Units Output Low Voltage I/O Pins: 4x Sink Driver Pins – RA0-RA2, RB0-RB2, RB5-RB10, RB15, RC1, RC2, RC9, RC10 — — 0.4 V IOL 6 mA, VDD = 3.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-11: ELECTRICAL CHARACTERISTICS: BOR DC CHARACTERISTICS Param No. Symbol Standard Operating Conditions (see Note 3): 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Characteristic Min(1) Typ Max Units 2.55 — 2.79 V Conditions See Note 2 BO10 VBOR Note 1: 2: 3: Parameters are for design guidance only and are not tested in manufacturing.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-12: DC CHARACTERISTICS: PROGRAM MEMORY Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param Symbol No. Characteristic Min Typ(1) Max Units Conditions Program Flash Memory D130 EP Cell Endurance 10,000 — — D131 VPR VDD for Read VMIN — 3.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 24.2 AC Characteristics and Timing Parameters This section defines dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 AC characteristics and timing parameters. TABLE 24-14: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Operating voltage VDD range as described in Table 24-1.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-2: EXTERNAL CLOCK TIMING Q1 Q2 Q3 Q4 Q1 Q2 OS30 OS30 Q3 Q4 OSC1 OS20 OS31 OS31 OS25 CLKO OS41 OS40 TABLE 24-16: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-17: PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 3.6V) AC CHARACTERISTICS Param No. Symbol Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Characteristic Min Typ(1) Max Units OS50 FPLLI PLL Voltage Controlled Oscillator (VCO) Input Frequency Range 0.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-19: AC CHARACTERISTICS: INTERNAL FRC ACCURACY AC CHARACTERISTICS Param No. Characteristic Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for Extended Min Typ Max Units Conditions Internal FRC Accuracy @ FRC Frequency = 7.37 MHz(1) F20a FRC -2 — +2 % -40°C TA +85°C VDD = 3.0-3.6V F20b FRC -5 — +5 % -40°C TA +125°C VDD = 3.0-3.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-3: I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) New Value Old Value DO31 DO32 Note: Refer to Figure 24-1 for load conditions. TABLE 24-21: I/O TIMING REQUIREMENTS AC CHARACTERISTICS Param No. Standard Operating Conditions: 3.0V to 3.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-4: VDD RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING CHARACTERISTICS SY12 MCLR SY10 Internal POR SY11 PWRT Time-out OSC Time-out SY30 Internal Reset Watchdog Timer Reset SY13 SY20 SY13 I/O Pins FSCM Delay SY35 Note: Refer to Figure 24-1 for load conditions. 2008-2014 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-22: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param Symbol No.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-5: TIMER1, 2 AND 3 EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx11 Tx10 Tx15 OS60 Tx20 TMRx Note: Refer to Figure 24-1 for load conditions. TABLE 24-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-24: TIMER2 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ. Max.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-6: INPUT CAPTURE x (ICx) TIMING CHARACTERISTICS ICx IC11 IC10 IC15 Note: Refer to Figure 24-1 for load conditions. TABLE 24-26: INPUT CAPTURE x TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-8: OCx/PWMx MODULE TIMING CHARACTERISTICS OC20 OCFA OC15 Active OCx Tri-State TABLE 24-28: SIMPLE OCx/PWMx MODE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-9: HIGH-SPEED PWMx MODULE FAULT TIMING CHARACTERISTICS MP30 FLTx MP20 PWMx FIGURE 24-10: HIGH-SPEED PWMx MODULE TIMING CHARACTERISTICS MP11 MP10 PWMx Note: Refer to Figure 24-1 for load conditions. TABLE 24-29: HIGH-SPEED PWMx MODULE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-30: SPIx MAXIMUM DATA/CLOCK RATE SUMMARY Standard Operating Conditions: 3.0V to 3.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-31: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-13: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING CHARACTERISTICS SP36 SCKx (CKP = 0) SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 Bit 14 - - - - - -1 MSb SDOx SP30, SP31 SP40 SDIx LSb MSb In LSb In Bit 14 - - - -1 SP41 Note: Refer to Figure 24-1 for load conditions. TABLE 24-32: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-14: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING CHARACTERISTICS SCKx (CKP = 0) SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 Bit 14 - - - - - -1 MSb SDOx SP30, SP31 SP30, SP31 SDIx MSb In LSb LSb In Bit 14 - - - -1 SP40 SP41 Note: Refer to Figure 24-1 for load conditions. TABLE 24-33: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-15: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING CHARACTERISTICS SP60 SSx SP52 SP50 SCKx (CKP = 0) SP70 SP73 SP72 SP72 SP73 SCKx (CKP = 1) SP35 MSb SDOx Bit 14 - - - - - -1 LSb SP30, SP31 SDIx MSb In Bit 14 - - - -1 SP51 LSb In SP41 SP40 Note: Refer to Figure 24-1 for load conditions. DS70000318G-page 316 2008-2014 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-34: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-16: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING CHARACTERISTICS SP60 SSx SP52 SP50 SCKx (CKP = 0) SP70 SP73 SP72 SP72 SP73 SCKx (CKP = 1) SP35 SP52 MSb SDOx Bit 14 - - - - - -1 LSb SP30, SP31 SDIx MSb In Bit 14 - - - -1 SP51 LSb In SP41 SP40 Note: Refer to Figure 24-1 for load conditions. DS70000318G-page 318 2008-2014 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-35: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-17: SPIx SLAVE MODE (FULL-DUPLEX CKE = 0, CKP = 1, SMP = 0) TIMING CHARACTERISTICS SSX SP52 SP50 SCKX (CKP = 0) SP70 SP73 SP72 SP72 SP73 SCKX (CKP = 1) SP35 SDOX Bit 14 - - - - - -1 MSb LSb SP51 SP30, SP31 SDIX MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure 24-1 for load conditions. DS70000318G-page 320 2008-2014 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-36: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-18: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING CHARACTERISTICS SSX SP52 SP50 SCKX (CKP = 0) SP70 SP73 SP72 SP72 SP73 SCKX (CKP = 1) SP35 SDOx Bit 14 - - - - - -1 MSb LSb SP51 SP30, SP31 SDIx MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure 24-1 for load conditions. DS70000318G-page 322 2008-2014 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-37: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-19: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCLx IM31 IM34 IM30 IM33 SDAx Start Condition Stop Condition Note: Refer to Figure 24-1 for load conditions. FIGURE 24-20: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM21 IM11 IM10 SCLx IM11 IM26 IM10 IM25 IM33 SDAx In IM40 IM40 IM45 SDAx Out Note: Refer to Figure 24-1 for load conditions. DS70000318G-page 324 2008-2014 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-38: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param Symbol No.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-21: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCLx IS34 IS31 IS30 IS33 SDAx Start Condition FIGURE 24-22: Stop Condition I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS21 IS11 IS10 SCLx IS30 IS26 IS31 IS25 IS33 SDAx In IS40 IS40 IS45 SDAx Out DS70000318G-page 326 2008-2014 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-39: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 = TABLE 24-40: 10-BIT HIGH-SPEED ADC MODULE SPECIFICATIONS Standard Operating Conditions (see Note 2): 3.0V and 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param Symbol No.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-41: 10-BIT, HIGH-SPEED ADC MODULE TIMING REQUIREMENTS Standard Operating Conditions (see Note 2): 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param Symbol No. Characteristic Min. Typ(1) Max. Units — ns — — Conditions Clock Parameters AD50b TAD ADC Clock Period AD55b tCONV Conversion Time AD56b FCNV Throughput Rate 35.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-42: COMPARATOR MODULE SPECIFICATIONS DC CHARACTERISTICS Standard Operating Conditions (see Note 2): 3.0V to 3.6V Operating temperature: -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Param. Symbol No. Characteristic Min Typ Max Units CM10 VIOFF Input Offset Voltage -58 +14/-40 66 mV CM11 VICM Input Common-Mode Voltage Range(1) 0 — AVDD – 1.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-44: DAC OUTPUT BUFFER DC SPECIFICATIONS DC CHARACTERISTICS Param. Symbol No. Characteristic Standard Operating Conditions (see Note 1): 3.0V to 3.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70000318G-page 332 2008-2014 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 25.0 HIGH-TEMPERATURE ELECTRICAL CHARACTERISTICS This section provides an overview of dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 electrical characteristics for devices operating in an ambient temperature range of -40°C to +150°C. Note: Programming of the Flash memory is not allowed above +125°C. The specifications between -40°C to +150°C are identical to those shown in Section 24.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 25.1 High-Temperature DC Characteristics TABLE 25-1: OPERATING MIPS VS. VOLTAGE Max MIPS Characteristic VDD Range (in Volts) Temperature Range (in °C) — 3.0V to 3.6V(1) -40°C to +150°C Note 1: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 20 Overall functional device operation at VBORMIN < VDD < VDDMIN is tested but not characterized. All device analog modules such as the ADC, etc., will function but with degraded performance below VDDMIN.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 25-4: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +150°C for High Temperature DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions Power-Down Current (IPD)(2,4) HDC60e 1000 2000 A +150°C 3.3V Base Power-Down Current HDC61c 100 110 A +150°C 3.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 25-5: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +150°C for High Temperature DC CHARACTERISTICS Param. Symbol DO10 DO20 VOL VOH Characteristic Min. Typ. Max. Units Conditions Output Low Voltage I/O Pins: 4x Sink Driver Pins – RA0-RA2, RB0-RB2, RB5RB10, RB15, RC1, RC2, RC9, RC10 — — 0.4 V IOL 3.6 mA, VDD = 3.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 25-6: DC CHARACTERISTICS: PROGRAM MEMORY DC CHARACTERISTICS Param Symbol No. Characteristic(1) Standard Operating Conditions: 3.0V to 3.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 25.2 AC Characteristics and Timing Parameters Parameters in this section begin with an H, which denotes High temperature. For example, Parameter OS53 in Section 24.2 “AC Characteristics and Timing Parameters” is the Industrial and Extended temperature equivalent of HOS53. The information contained in this section defines dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 AC characteristics and timing parameters for hightemperature devices.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 25-9: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS AC CHARACTERISTICS Param No. Symbol Standard Operating Conditions: 3.0V to 3.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 25-11: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS AC CHARACTERISTICS Param No. Symbol Standard Operating Conditions: 3.0V to 3.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 26.0 50 MIPS ELECTRICAL CHARACTERISTICS This section provides an overview of dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 electrical characteristics for devices operating at 50 MIPS. The specifications for 50 MIPS are identical to those shown in Section 24.0 “Electrical Characteristics”, with the exception of the parameters listed in this section. Parameters in this section begin with the letter “M”, which denotes 50 MIPS operation.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 26.1 DC Characteristics TABLE 26-1: OPERATING MIPS VS. VOLTAGE Max MIPS Characteristic VDD Range (in Volts) Temp Range (in °C) — 3.0-3.6V(1) -40°C to +85°C Note 1: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 50 Overall functional device operation at VBORMIN < VDD < VDDMIN is tested but not characterized. All device analog modules, such as the ADC, etc., will function but with degraded performance below VDDMIN.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 26-3: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial DC CHARACTERISTICS Parameter No. Typical Max Units Conditions Idle Current (IIDLE): Core Off, Clock On Base Current(1) MDC45d 64 105 mA -40°C MDC45a 64 105 mA +25°C MDC45b 64 105 mA +85°C Note 1: 3.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 26-4: DC CHARACTERISTICS: DOZE CURRENT (IDOZE)(1) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial DC CHARACTERISTICS Parameter No.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 26.2 AC Characteristics and Timing Parameters This section defines the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 AC characteristics and timing parameters for 50 MIPS devices. TABLE 26-5: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial AC CHARACTERISTICS Param No.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70000318G-page 346 2008-2014 Microchip Technology Inc.
DC AND AC DEVICE CHARACTERISTICS GRAPHS Note: The graphs provided following this note are a statistical summary based on a limited number of samples and are provided for design guidance purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. FIGURE 27-1: VOH – 4x DRIVER PINS -0.080 -0.030 3.6V -0.
VOL – 4x DRIVER PINS FIGURE 27-6: 0.120 0.040 0.035 3.6V 0.030 3.6V 0.100 3.3V 0.025 3.3V 0.080 3V IOL (A) IOL (A) VOL – 16x DRIVER PINS 0.020 0.015 Absolute Maximum 3V 0.060 Absolute Maximum 0.040 0.010 0.020 0.005 0.000 0.00 1.00 2.00 3.00 4.00 VOL (V) FIGURE 27-5: 0.060 3.6V 0.050 3.3V IOL (A) 2008-2014 Microchip Technology Inc. 3V 0.030 Absolute Maximum 0.020 0.010 0.000 0.00 1.00 2.00 VOL (V) 1.00 2.00 VOL (V) VOL – 8x DRIVER PINS 0.040 0.000 0.00 3.00 4.
TYPICAL IPD CURRENT @ VDD = 3.3V FIGURE 27-9: 1220 118 108 1020 98 IDO OZE Current (mA) IPD Current (µA) TYPICAL IDOZE CURRENT @ VDD = 3.3V 820 620 420 88 78 68 50 MIPS 58 40 MIPS 48 38 220 28 20 -40 25 65 85 125 18 150 1:1 1:2 Temperature (Celsius) FIGURE 27-8: 1:64 1:128 Doze Ratio TYPICAL IDD CURRENT @ VDD = 3.3V FIGURE 27-10: 120 TYPICAL IIDLE CURRENT @ VDD = 3.
TYPICAL FRC FREQUENCY @ VDD = 3.3V FIGURE 27-13: 7.45 1.36 1.35 7.35 1.34 7.3 INTREF (V) FRC Frequency (MHz) 7.4 7.25 7.2 7.15 1.33 1.32 1.31 7.1 71 1.3 7.05 7 1.29 -40 25 85 125 150 FIGURE 27-12: TYPICAL LPRC FREQUENCY @ VDD = 3.3V 34 32 30 2008-2014 Microchip Technology Inc. 28 26 24 22 20 18 -40 25 85 Temperature (Celsius) -40 25 85 Temperature (Celsius) Temperature (Celsius) LPRC Frequency (kHz) TYPICAL INTREF @ VDD = 3.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 28.0 PACKAGING INFORMATION 28.1 Package Marking Information 18-Lead SOIC (.
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dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 28.2 Note: Package Details For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2008-2014 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70000318G-page 354 2008-2014 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2008-2014 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70000318G-page 356 2008-2014 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2008-2014 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70000318G-page 358 2008-2014 Microchip Technology Inc.
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dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 28-Lead Plastic Quad Flat, No Lead Package (MX) - 6x6x0.5mm Body [UQFN] Ultra-Thin with 0.40 x 0.60 mm Terminal Width/Length and Corner Anchors Note: )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ ' $ % 1 127( '$780 $ ( '$780 % ; & ; & 723 9,(: $ & & 6($7,1* 3/$1( $ $ E 127( & 6,'( 9,(: ' & $ % H ( .
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dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Note: )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ DS70000318G-page 364 2008-2014 Microchip Technology Inc.
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dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 2008-2014 Microchip Technology Inc.
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dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 44-Terminal Very Thin Leadless Array Package (TL) – 6x6x0.9 mm Body With Exposed Pad [VTLA] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A N NOTE 1 B 1 2 E (DATUM B) 2X 0.20 C 2X (DATUM A) 0.20 C C SEATING PLANE TOP VIEW 0.10 C A1 A 0.08 C SIDE VIEW 0.10 D2 11 C A B 22 0.
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dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 DS70000318G-page 372 2008-2014 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 APPENDIX A: REVISION HISTORY Revision A (January 2008) This is the initial revision of this document. Revision B (June 2008) This revision includes minor typographical and formatting changes throughout the data sheet text. In addition, redundant information was removed that is now available in the respective chapters of the dsPIC33F/PIC24H Family Reference Manual, which can be obtained from the Microchip web site (www.microchip.com).
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE A-1: MAJOR SECTION UPDATES (CONTINUED) Section Name Section 7.0 “Oscillator Configuration” Update Description Removed the first sentence of the third clock source item (External Clock) in Section 7.1.1 “System Clock sources” Updated the default bit values for DOZE and FRCDIV in the Clock Divisor Register (see Register 7-2). Section 8.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE A-1: MAJOR SECTION UPDATES (CONTINUED) Section Name Section 16.0 “Inter-Integrated Circuit (I2C™)” Update Description Removed the following sections, which are now available in the related section of the dsPIC33F/PIC24H Family Reference Manual: • 16.3 “I2C Interrupts” • 16.4 “Baud Rate Generator” (retained Figure 16-1: I2C Block Diagram) • 16.5 “I2C Module Addresses • 16.6 “Slave Address Masking” • 16.7 “IPMI Support” • 16.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE A-1: MAJOR SECTION UPDATES (CONTINUED) Section Name Section 23.0 “Electrical Characteristics” Update Description Updated Typ values for Thermal Packaging Characteristics (Table 23-3). Removed Typ value for DC Temperature and Voltage Specifications Parameter DC12 (Table 23-4). Updated all Typ values and conditions for DC Characteristics: Operating Current (IDD), updated last sentence in Note 2 (Table 23-5).
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Revision C and D (March 2009) This revision includes minor typographical and formatting changes throughout the data sheet text. Global changes include: • Changed all instances of OSCI to OSC1 and OSCO to OSC2 • Changed all instances of PGCx/EMUCx and PGDx/EMUDx (where x = 1, 2, or 3) to PGECx and PGEDx • Changed all instances of VDDCORE and VDDCORE/ VCAP to VCAP/VDDCORE Other major changes are referenced by their respective section in the following table.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE A-2: MAJOR SECTION UPDATES (CONTINUED) Section Name Section 8.0 “Oscillator Configuration” Update Description Added Note 2 to the Oscillator System Diagram (see Figure 8-1). Added a paragraph regarding FRC accuracy at the end of Section 8.1.1 “System Clock Sources”. Added Note 1 and Note 2 to the OSCON register (see Register ). Added Note 1 to the OSCTUN register (see Register 8-4). Added Note 3 to Section 8.4.2 “Oscillator Switching Sequence”.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE A-2: MAJOR SECTION UPDATES (CONTINUED) Section Name Section 24.0 “Electrical Characteristics” Update Description Updated Typical values for Thermal Packaging Characteristics (see Table 24-3). Updated Min and Max values for Parameter DC12 (RAM Data Retention Voltage) and added Note 4 (see Table 24-4). Updated Characteristics for I/O Pin Input Specifications (see Table 24-9). Added ISOURCE to I/O Pin Output Specifications (see Table 24-10).
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Revision E (December 2009) The revision includes the following global update: • Added Note 2 to the shaded table that appears at the beginning of each chapter. This new note provides information regarding the availability of registers and their associated bits This revision also includes minor typographical and formatting changes throughout the data sheet text. All other major changes are referenced by their respective section in the following table.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE A-3: MAJOR SECTION UPDATES (CONTINUED) Section Name Section 19.0 “High-Speed 10-bit Analog-to-Digital Converter (ADC)” Update Description Updated Note 1 in the ADCPC0 register (see Register 19-5). Updated Note 3 in the ADCPC1 register (see Register 19-6). Updated Note 2 in the ADCPC2 and ADCPC3 registers (see Register 197 and Register 19-8). Section 21.0 “Special Features” Updated the second paragraph and removed the fourth paragraph in Section 21.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Revision F (January 2012) All occurrences of VDDCORE have been removed throughout the document. This revision also includes minor typographical and formatting changes throughout the data sheet text. All other major changes are referenced by their respective section in the following table.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE A-4: MAJOR SECTION UPDATES (CONTINUED) Section Name Section 24.0 “Electrical Characteristics” Update Description Updated the Absolute Maximum Ratings. Updated the Operating MIPS vs. Voltage (see Table 24-1). Updated Parameter DC10 and Note 4, and removed Parameter DC18 from the DC Temperature and Voltage Specifications (see Table 24-4). Updated Note 2 in the IDD Operating Current specification (see Table 24-5).
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE A-4: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description Section 26.0 “50 MIPS Electrical Characteristics” Added new chapter in support of 50 MIPS devices. Section 27.0 “DC and AC Device Characteristics Graphs” Added new chapter. Section 28.0 “Packaging Information” Added 44-pin VTLA package marking information and diagrams (see Section 28.1 “Package Marking Information” and Section 28.2 “Package Details”, respectively).
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Revision G (May 2014) The values for the TUN<5:0> bits in Register 8-4 (OSCTUN) have changed. The DC Characteristics Idle Current values in Section 24.0 “Electrical Characteristics” have been updated. The timer specifications in Section 26.0 “50 MIPS Electrical Characteristics” have been removed. All diagrams in Section 28.0 “Packaging Information” have been updated. Minor text edits have been applied throughout the document.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70000318G-page 386 2008-2014 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 INDEX A AC Characteristics ............................................ 300, 338, 345 Internal FRC Accuracy.............................................. 303 Internal LPRC Accuracy............................................ 303 Load Conditions ................................................ 300, 338 ADC Control Registers ...................................................... 246 Functionality..............................................................
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Demo/Development Boards, Evaluation and Starter Kits ................................................................ 286 Development Support ....................................................... 283 Third-Party Tools ...................................................... 286 Doze Mode........................................................................ 148 DSP Engine......................................................................... 38 Multiplier....
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 P Packaging ......................................................................... 351 Details ....................................................................... 353 Marking ..................................................................... 351 Peripheral Module Disable (PMD) .................................... 148 Peripheral Pin Select (PPS) .............................................. 157 PICkit 3 In-Circuit Debugger/Programmer ..................
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 IFS5 (Interrupt Flag Status 5) ................................... 109 IFS6 (Interrupt Flag Status 6) ................................... 110 IFS7 (Interrupt Flag Status 7) ................................... 111 INTCON1 (Interrupt Control 1) .................................. 102 INTTREG (Interrupt Control and Status)................... 133 IOCONx (PWMx I/O Control) .................................... 212 IPC0 (Interrupt Priority Control 0) ...................
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Timing Diagrams Analog-to-Digital Conversion per Input ..................... 329 Brown-out Situations................................................... 94 External Clock........................................................... 301 High-Speed PWMx ................................................... 311 High-Speed PWMx Fault .......................................... 311 I/O .............................................................................
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dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70000318G-page 394 2008-2014 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. dsPIC 33 FJ 06 GS1 02 T - 50 E / SP - XXX Examples: a) dsPIC33FJ06GS102-E/SP: SMPS dsPIC33, 6-Kbyte program memory, 28-pin, Extended temperature, SPDIP package.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70000318G-page 396 2008-2014 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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