Datasheet

© 2007 Microchip Technology Inc. Preliminary DS70165E-page 361
dsPIC33F
Instruction-Based Power-Saving Modes........................... 157
Idle ............................................................................158
Sleep.........................................................................157
Internal RC Oscillator
Use with WDT...........................................................294
Internet Address................................................................ 365
Interrupt Control and Status Registers................................ 91
IECx ............................................................................91
IFSx.............................................................................91
INTCON1 ....................................................................91
INTCON2 ....................................................................91
IPCx ............................................................................91
Interrupt Setup Procedures............................................... 133
Initialization............................................................... 133
Interrupt Disable........................................................133
Interrupt Service Routine .......................................... 133
Trap Service Routine ................................................133
Interrupt Vector Table (IVT) ................................................87
Interrupts Coincident with Power Save Instructions.......... 158
J
JTAG Boundary Scan Interface ........................................ 289
M
Memory Organization.......................................................... 39
Microchip Internet Web Site..............................................365
Modes of Operation
Disable......................................................................233
Initialization............................................................... 233
Listen All Messages.................................................. 233
Listen Only................................................................233
Loopback .................................................................. 233
Normal Operation...................................................... 233
Modulo Addressing .............................................................68
Applicability................................................................. 70
Operation Example .....................................................69
Start and End Address................................................ 69
W Address Register Selection .................................... 69
Motor Control PWM ..........................................................175
Motor Control PWM Module
8-Output Register Map................................................ 52
MPLAB ASM30 Assembler, Linker, Librarian ................... 306
MPLAB ICD 2 In-Circuit Debugger ................................... 307
MPLAB ICE 2000 High-Performance Universal
In-Circuit Emulator .................................................... 307
MPLAB ICE 4000 High-Performance Universal
In-Circuit Emulator .................................................... 307
MPLAB Integrated Development Environment
Software....................................................................305
MPLAB PM3 Device Programmer ....................................307
MPLINK Object Linker/MPLIB Object Librarian ................ 306
N
NVM Module
Register Map............................................................... 66
O
Open-Drain Configuration ................................................. 160
Output Compare ............................................................... 171
Registers................................................................... 174
P
Packaging .........................................................................351
Details.......................................................................352
Marking..................................................................... 351
Peripheral Module Disable (PMD) ....................................158
PICSTART Plus Development Programmer..................... 308
Pinout I/O Descriptions (table)............................................ 25
PMD Module
Register Map .............................................................. 66
POR and Long Oscillator Start-up Times ........................... 86
PORTA
Register Map .............................................................. 64
PORTB
Register Map .............................................................. 64
PORTC
Register Map .............................................................. 65
PORTD
Register Map .............................................................. 65
PORTE
Register Map .............................................................. 65
PORTF
Register Map .............................................................. 65
PORTG
Register Map .............................................................. 66
Power-Saving Features.................................................... 157
Clock Frequency and Switching ............................... 157
Program Address Space..................................................... 39
Construction ............................................................... 72
Data Access from Program Memory Using
Program Space Visibility.................................... 75
Data Access from Program Memory Using
Table Instructions ............................................... 74
Data Access from, Address Generation ..................... 73
Memory Map............................................................... 39
Table Read Instructions
TBLRDH ............................................................. 74
TBLRDL.............................................................. 74
Visibility Operation...................................................... 75
Program Memory
Interrupt Vector........................................................... 40
Organization ............................................................... 40
Reset Vector............................................................... 40
Pulse-Width Modulation Mode.......................................... 172
PWM
Center-Aligned.......................................................... 179
Complementary Mode .............................................. 180
Complementary Output Mode .................................. 181
Duty Cycle ................................................................ 172
Edge-Aligned............................................................ 178
Independent Output Mode........................................ 181
Operation During CPU Idle Mode............................. 183
Operation During CPU Sleep Mode ......................... 183
Output Override........................................................ 181
Output Override Synchronization ............................. 182
Period ............................................................... 172, 178
Single Pulse Mode.................................................... 181
PWM Dead-Time Generators ........................................... 180
Assignment............................................................... 181
Ranges ..................................................................... 181
Selection Bits (table)................................................. 181
PWM Duty Cycle
Comparison Units..................................................... 179
Immediate Updates .................................................. 179
Register Buffers........................................................ 179
PWM Fault Pins................................................................ 182
Enable Bits ............................................................... 182
Fault States .............................................................. 182
Input Modes.............................................................. 183
Cycle-by-Cycle ................................................. 183
Latched............................................................. 183