Datasheet

© 2007 Microchip Technology Inc. Preliminary DS70165E-page 359
dsPIC33F
INDEX
A
A/D Converter ................................................................... 275
DMA..........................................................................275
Initialization............................................................... 275
Key Features.............................................................275
AC Characteristics ............................................................ 316
Internal RC Accuracy................................................318
Load Conditions........................................................ 316
AC-Link Mode Operation .................................................. 268
16-bit Mode............................................................... 268
20-bit Mode............................................................... 269
ADC Module
ADC11 Register Map..................................................55
ADC2 Register Map.................................................... 55
Alternate Vector Table (AIVT).............................................87
Arithmetic Logic Unit (ALU).................................................33
Assembler
MPASM Assembler...................................................306
Automatic Clock Stretch....................................................215
Receive Mode...........................................................215
Transmit Mode.......................................................... 215
B
Barrel Shifter ....................................................................... 37
Bit-Reversed Addressing ....................................................70
Example...................................................................... 71
Implementation ...........................................................70
Sequence Table (16-Entry)......................................... 71
Block Diagrams
16-bit Timer1 Module................................................ 161
A/D Module ....................................................... 276, 277
Connections for On-Chip Voltage Regulator.............293
DCI Module............................................................... 261
Device Clock..................................................... 149, 151
DSP Engine ................................................................34
dsPIC33F....................................................................24
dsPIC33F CPU Core................................................... 28
ECAN Module ...........................................................231
Input Capture ............................................................ 169
Output Compare .......................................................173
PLL............................................................................ 151
PWM Module ............................................................ 176
Quadrature Encoder Interface ..................................197
Reset System..............................................................83
Shared Port Structure ............................................... 159
SPI ............................................................................206
Timer2 (16-bit) .......................................................... 165
Timer2/3 (32-bit) .......................................................164
UART ........................................................................223
Watchdog Timer (WDT)............................................ 294
C
C Compilers
MPLAB C18 .............................................................. 306
MPLAB C30 .............................................................. 306
Clock Switching................................................................. 156
Enabling....................................................................156
Sequence.................................................................. 156
Code Examples
DMA Sample Initialization Method ............................ 139
Erasing a Program Memory Page............................... 80
Initiating a Programming Sequence............................ 81
Loading Write Buffers ................................................. 81
Port Write/Read........................................................ 160
PWRSAV Instruction Syntax .................................... 157
Code Protection........................................................ 289, 295
Configuration Bits ............................................................. 289
Description (Table) ................................................... 290
Configuration Register Map.............................................. 289
Configuring Analog Port Pins............................................ 160
CPU
Control Register.......................................................... 30
CPU Clocking System ...................................................... 150
Options ..................................................................... 150
Selection................................................................... 150
Customer Change Notification Service............................. 365
Customer Notification Service .......................................... 365
Customer Support............................................................. 365
D
Data Accumulators and Adder/Subtractor .......................... 35
Data Space Write Saturation...................................... 37
Overflow and Saturation............................................. 35
Round Logic ............................................................... 36
Write Back .................................................................. 36
Data Address Space........................................................... 41
Alignment.................................................................... 41
Memory Map for dsPIC33F Devices with
16 KBs RAM....................................................... 43
Memory Map for dsPIC33F Devices with
30 KBs RAM....................................................... 44
Memory Map for dsPIC33F Devices with
8 KBs RAM......................................................... 42
Near Data Space........................................................ 41
Software Stack ........................................................... 67
Width .......................................................................... 41
Data Converter Interface (DCI) Module............................ 261
DC Characteristics............................................................ 310
I/O Pin Input Specifications ...................................... 314
I/O Pin Output Specifications.................................... 315
Idle Current (I
DOZE) .................................................. 313
Idle Current (I
IDLE).................................................... 312
Operating Current (I
DD) ............................................ 311
Power-Down Current (I
PD)........................................ 312
Program Memory...................................................... 315
Temperature and Voltage Specifications.................. 310
DCI
Bit Clock Generator .................................................. 265
Buffer Alignment with Data Frames.......................... 267
Buffer Control ........................................................... 261
Buffer Data Alignment .............................................. 261
Buffer Length Control ............................................... 267
CSDO Mode Bit........................................................ 268
Data Justification Control Bit .................................... 266
Device Frequencies for Common Codec
CSCK Frequencies (Table) .............................. 265
Digital Loopback Mode............................................. 268
Frame Sync Generator............................................. 263
Frame Sync Mode Control Bits................................. 263
Interrupts .................................................................. 268
Introduction............................................................... 261
Master Frame Sync Operation ................................. 263
Module Enable.......................................................... 263
Operation.................................................................. 263
Operation During CPU Idle Mode............................. 268
Operation During CPU Sleep Mode ......................... 268
Receive Slot Enable Bits .......................................... 266