Datasheet

dsPIC33F
DS70165E-page 178 Preliminary © 2007 Microchip Technology Inc.
15.1.4 DOUBLE UPDATE MODE
In the Double Update mode (PTMOD<1:0> = 11), an
interrupt event is generated each time the PTMR regis-
ter is equal to zero, as well as each time a period match
occurs. The postscaler selection bits have no effect in
this mode of the timer.
The Double Update mode provides two additional
functions to the user. First, the control loop bandwidth is
doubled because the PWM duty cycles can be updated,
twice per period. Second, asymmetrical center-aligned
PWM waveforms can be generated, which are useful for
minimizing output waveform distortion in certain motor
control applications.
15.1.5 PWM TIME BASE PRESCALER
The input clock to PTMR (FOSC/4) has prescaler
options of 1:1, 1:4, 1:16 or 1:64, selected by control
bits, PTCKPS<1:0>, in the PTCON SFR. The prescaler
counter is cleared when any of the following occurs:
• a write to the PTMR register
• a write to the PTCON register
• any device Reset
The PTMR register is not cleared when PTCON is
written.
15.1.6 PWM TIME BASE POSTSCALER
The match output of PTMR can optionally be post-
scaled through a 4-bit postscaler (which gives a 1:1 to
1:16 scaling).
The postscaler counter is cleared when any of the
following occurs:
• a write to the PTMR register
• a write to the PTCON register
• any device Reset
The PTMR register is not cleared when PTCON is written.
15.2 PWM Period
PTPER is a 15-bit register and is used to set the counting
period for the PWM time base. PTPER is a double-
buffered register. The PTPER buffer contents are loaded
into the PTPER register at the following instants:
• Free-Running and Single-Shot modes:
When the
PTMR register is reset to zero after a match with
the PTPER register.
• Up/Down Count modes: When the PTMR register
is zero.
The value held in the PTPER buffer is automatically
loaded into the PTPER register when the PWM time
base is disabled (PTEN = 0).
The PWM period can be determined using
Equation 15-1:
EQUATION 15-1: PWM PERIOD
If the PWM time base is configured for one of the Up/
Down Count modes, the PWM period will be twice the
value provided by Equation 15-1.
The maximum resolution (in bits) for a given device
oscillator and PWM frequency can be determined using
Equation 15-2:
EQUATION 15-2: PWM RESOLUTION
15.3 Edge-Aligned PWM
Edge-aligned PWM signals are produced by the module
when the PWM time base is in Free-Running or Single-
Shot mode. For edge-aligned PWM outputs, the output
has a period specified by the value in PTPER and a duty
cycle specified by the appropriate Duty Cycle register
(see Figure 15-2). The PWM output is driven active at
the beginning of the period (PTMR = 0) and is driven
inactive when the value in the Duty Cycle register
matches PTMR.
If the value in a particular Duty Cycle register is zero,
then the output on the corresponding PWM pin will be
inactive for the entire PWM period. In addition, the out-
put on the PWM pin will be active for the entire PWM
period if the value in the Duty Cycle register is greater
than the value held in the PTPER register.
FIGURE 15-2: EDGE-ALIGNED PWM
Note: Programming a value of 0x0001 in the
PWM Period register could generate a
continuous interrupt pulse and hence,
must be avoided.
TPWM =
T
CY • (PTPER + 1)
(PTMR Prescale Value)
Resolution =
log (2 • T
PWM/TCY)
log (2)
Period
Duty Cycle
0
PTPER
PTMR
Value
New Duty Cycle Latched