Datasheet

© 2007 Microchip Technology Inc. Preliminary DS70165E-page 149
dsPIC33F
8.0 OSCILLATOR
CONFIGURATION
The dsPIC33F oscillator system provides:
• Various external and internal oscillator options as
clock sources
• An on-chip PLL to scale the internal operating
frequency to the required system clock frequency
• The internal FRC oscillator can also be used with
the PLL, thereby allowing full-speed operation
without any external clock generation hardware
• Clock switching between various clock sources
• Programmable clock postscaler for system power
savings
• A Fail-Safe Clock Monitor (FSCM) that detects
clock failure and takes fail-safe measures
• A Clock Control register (OSCCON)
• Nonvolatile Configuration bits for main oscillator
selection.
A simplified diagram of the oscillator system is shown
in Figure 8-1.
FIGURE 8-1: dsPIC33F OSCILLATOR SYSTEM DIAGRAM
Note: This data sheet summarizes the features
of this group of dsPIC33F devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “dsPIC30F
Family Reference Manual” (DS70046).
dsPIC33F
PLL
Secondary Oscillator
SOSCEN
Enable
Oscillator
SOSCO
SOSCI
Clock Source Option
for other Modules
OSC1
OSC2
Primary Oscillator
XTPLL, HSPLL,
XT, HS, EC
CPU
Peripherals
/FRCDIIV
FRCDIV<2:0>
WDT, PWRT
FRC, FRCDIVN
FRC
Oscillator
LPRC
Oscillator
SOSC
LPRC
/DOZE
Clock Control Logic
Fail-Safe
Clock
Monitor
DOZE<2:0>
ECPLL, FRCPLL
Divide
By 16
FRCDIV16