dsPIC33F Family Data Sheet High-Performance, 16-Bit Digital Signal Controllers © 2007 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
dsPIC33F High-Performance, 16-bit Digital Signal Controllers Operating Range: Digital I/O: • DC – 40 MIPS (40 MIPS @ 3.0-3.
dsPIC33F Communication Modules: Motor Control Peripherals: • 3-wire SPI (up to 2 modules): - Framing supports I/O interface to simple codecs - Supports 8-bit and 16-bit data - Supports all serial clock formats and sampling modes • I2C™ (up to 2 modules): - Full Multi-Master Slave mode support - 7-bit and 10-bit addressing - Bus collision detection and arbitration - Integrated signal conditioning - Slave address masking • UART (up to 2 modules): - Interrupt on address bit detect - Interrupt on UART error -
dsPIC33F dsPIC33F PRODUCT FAMILIES for Uninterrupted Power Supply (UPS), inverters, Switched mode power supplies, power factor correction and also for controlling the power management module in servers, telecommunication equipment and other industrial equipment. There are two device subfamilies within the dsPIC33F family of devices. They are the General Purpose Family and the Motor Control Family. The General Purpose Family is ideal for a wide variety of 16-bit MCU embedded applications.
dsPIC33F Pin Diagrams 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 CSDO/RG13 CSDI/RG12 CSCK/RG14 RG0 RG1 RF1 RF0 VDD VDDCORE OC8/CN16/RD7 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1 64-Pin TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dsPIC33FJ64GP206 dsPIC33FJ128GP206 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 VSS OSC2/CLKO/RC15 OSC1/CLKIN
dsPIC33F Pin Diagrams (Continued) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 CSDO/RG13 CSDI/RG12 CSCK/RG14 RG0 RG1 RF1 RF0 VDD VDDCORE OC8/CN16/RD7 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1 64-Pin TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dsPIC33FJ64GP306 dsPIC33FJ128GP306 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 VSS OSC2/CLKO/RC1
dsPIC33F Pin Diagrams (Continued) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 CSDO/RG13 CSDI/RG12 CSCK/RG14 RG0 RG1 C1TX/RF1 C1RX/RF0 VDD VDDCORE OC8/CN16/RD7 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1 64-Pin TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dsPIC33FJ256GP506 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 VSS OSC2/CLKO/RC15 OSC1/
dsPIC33F Pin Diagrams (Continued) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 CSDO/RG13 CSDI/RG12 CSCK/RG14 C2RX/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VDD VDDCORE OC8/CN16/RD7 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1 64-Pin TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dsPIC33FJ64GP706 dsPIC33FJ128GP706 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/R
dsPIC33F Pin Diagrams (Continued) IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1 63 62 61 OC6/CN14/RD5 OC5/CN13/RD4 IC6/CN19/RD13 CSCK/RG14 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 OC7/CN15/RD6 CSDO/RG13 CSDI/RG12 80 79 AN23/CN23/RA7 AN22/CN22/RA6 C2RX/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VDD VDDCORE OC8/CN16/RD7 80-Pin TQFP 1 60 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 2 59 PGD2/EMUD2/SOSCI/CN1/RC13 OC1/RD0 AN18/T4CK/T9CK/RC3 3 4 58 57 IC4/RD11 AN19/T5CK/T8CK/RC4 5 56 IC3/RD10 SCK2/CN8/RG6 6 55 IC2/RD9 SD
dsPIC33F Pin Diagrams (Continued) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 AN28/RE4 AN27/RE3 AN26/RE2 CSDO/RG13 CSDI/RG12 CSCK/RG14 AN25/RE1 AN24/RE0 AN23/CN23/RA7 AN22/CN22/RA6 RG0 RG1 RF1 RF0 VDD VDDCORE OC8/CN16/RD7 OC7/CN15/RD6 OC6/CN14/RD5 OC5/CN13/RD4 IC6/CN19/RD13 IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1 100-Pin TQFP COFS/RG15 VDD AN29/RE5 AN30/RE6 AN31/RE7 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN18/T4CK/T9CK/RC3 AN19/T5CK/T8CK/RC4 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG
dsPIC33F Pin Diagrams (Continued) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 AN28/RE4 AN27/RE3 AN26/RE2 CSDO/RG13 CSDI/RG12 CSCK/RG14 AN25/RE1 AN24/RE0 AN23/CN23/RA7 AN22/CN22/RA6 RG0 RG1 C1TX/RF1 C1RX/RF0 VDD VDDCORE OC8/CN16/RD7 OC7/CN15/RD6 OC6/CN14/RD5 OC5/CN13/RD4 IC6/CN19/RD13 IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1 100-Pin TQFP COFS/RG15 VDD AN29/RE5 AN30/RE6 AN31/RE7 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN18/T4CK/T9CK/RC3 AN19/T5CK/T8CK/RC4 SCK2/CN8/RG6 SDI2/CN9/RG7 SD
dsPIC33F Pin Diagrams (Continued) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 AN28/RE4 AN27/RE3 AN26/RE2 CSDO/RG13 CSDI/RG12 CSCK/RG14 AN25/RE1 AN24/RE0 AN23/CN23/RA7 AN22/CN22/RA6 C2RX/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VDD VDDCORE OC8/CN16/RD7 OC7/CN15/RD6 OC6/CN14/RD5 OC5/CN13/RD4 IC6/CN19/RD13 IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1 100-Pin TQFP COFS/RG15 VDD AN29/RE5 AN30/RE6 AN31/RE7 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN18/T4CK/T9CK/RC3 AN19/T5CK/T8CK/RC4 SCK2/CN8/RG6 SDI2/
dsPIC33F Timer 16-bit Input Capture Output Compare Std.
dsPIC33F Pin Diagrams 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PWM3L/RE4 PWM2H/RE3 PWM2L/RE2 PWM1H/RE1 PWM1L/RE0 C1TX/RF1 C1RX/RF0 VDD VDDCORE OC8/UPDN/CN16/RD7 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1 64-Pin TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dsPIC33FJ64MC506 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/FLTB/INT2/RD9 IC1/FLTA/INT1/RD8 VSS OSC2/C
dsPIC33F Pin Diagrams (Continued) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PWM3L/RE4 PWM2H/RE3 PWM2L/RE2 PWM1H/RE1 PWM1L/RE0 C1TX/RF1 C1RX/RF0 VDD VDDCORE OC8/UPDN/CN16/RD7 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1 64-Pin TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dsPIC33FJ128MC506 dsPIC33FJ64MC506 dsPIC33FJ128MC706 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/
dsPIC33F Pin Diagrams (Continued) IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1 63 62 61 OC6/CN14/RD5 OC5/CN13/RD4 IC6/CN19/RD13 OC7/CN15/RD6 RG1 C1TX/RF1 C1RX/RF0 VDD VDDCORE OC8/CN16/UPDN/RD7 75 74 73 72 71 70 69 68 67 66 65 64 PWM2L/RE2 PWM1H/RE1 PWM1L/RE0 RG0 80 79 78 77 76 PWM3L/RE4 PWM2H/RE3 80-Pin TQFP PWM3H/RE5 1 60 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PWM4L/RE6 2 59 PGD2/EMUD2/SOSCI/CN1/RC13 OC1/RD0 PWM4H/RE7 3 58 AN16/T2CK/T7CK/RC1 4 57 IC4/RD11 AN17/T3CK/T6CK/RC2 5 56 IC3/RD10 SCK2/CN8/
dsPIC33F Pin Diagrams (Continued) OC2/RD1 IC5/RD12 OC4/RD3 OC3/RD2 OC8/CN16/UPDN/RD7 OC7/CN15/RD6 OC6/CN14/RD5 OC5/CN13/RD4 IC6/CN19/RD13 CRX2/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VDD VDDCORE 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PWM2L/RE2 PWM1H/RE1 PWM1L/RE0 80 79 78 77 76 PWM3L/RE4 PWM2H/RE3 80-Pin TQFP PWM3H/RE5 1 60 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PWM4L/RE6 2 59 PGD2/EMUD2/SOSCI/CN1/RC13 OC1/RD0 PWM4H/RE7 3 58 AN16/T2CK/T7CK/RC1 4 57 AN17/T3CK/T6CK/RC2 SCK2/CN8/RG6 5 56 IC4/RD
dsPIC33F Pin Diagrams (Continued) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PWM3L/RE4 PWM2H/RE3 PWM2L/RE2 CSDO/RG13 CSDI/RG12 CSCK/RG14 PWM1H/RE1 PWM1L/RE0 AN23/CN23/RA7 AN22/CN22/RA6 RG0 RG1 C1TX/RF1 C1RX/RF0 VDD VDDCORE OC8/UPDN//CN16/RD7 OC7/CN15/RD6 OC6/CN14/RD5 OC5/CN13/RD4 IC6/CN19/RD13 IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1 100-Pin TQFP COFS/RG15 VDD PWM3H/RE5 PWM4L/RE6 PWM4H/RE7 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN18/T4CK/T9CK/RC3 AN19/T5CK/T8CK/RC4 SCK2/CN8/RG6 S
dsPIC33F Pin Diagrams (Continued) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PWM3L/RE4 PWM2H/RE3 PWM2L/RE2 CSDO/RG13 CSDI/RG12 CSCK/RG14 PWM1H/RE1 PWM1L/RE0 AN23/CN23/RA7 AN22/CN22/RA6 RG0 RG1 C1TX/RF1 C1RX/RF0 VDD VDDCORE OC8/UPDN//CN16/RD7 OC7/CN15/RD6 OC6/CN14/RD5 OC5/CN13/RD4 IC6/CN19/RD13 IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1 100-Pin TQFP COFS/RG15 VDD PWM3H/RE5 PWM4L/RE6 PWM4H/RE7 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN18/T4CK/T9CK/RC3 AN19/T5CK/T8CK/RC4 SCK2/CN8/RG6 S
dsPIC33F Pin Diagrams (Continued) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PWM3L/RE4 PWM2H/RE3 PWM2L/RE2 CSDO/RG13 CSDI/RG12 CSCK/RG14 PWM1H/RE1 PWM1L/RE0 AN23/CN23/RA7 AN22/CN22/RA6 C2RX/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VDD VDDCORE OC8/UPDN//CN16/RD7 OC7/CN15/RD6 OC6/CN14/RD5 OC5/CN13/RD4 IC6/CN19/RD13 IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1 100-Pin TQFP COFS/RG15 VDD PWM3H/RE5 PWM4L/RE6 PWM4H/RE7 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN18/T4CK/T9CK/RC3 AN19/T5CK/T8CK/RC4 SCK2
dsPIC33F Table of Contents dsPIC33F Product Families ................................................................................................................................................................... 3 1.0 Device Overview ........................................................................................................................................................................ 23 2.0 CPU..............................................................................................
dsPIC33F TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.
dsPIC33F NOTES: DS70165E-page 22 Preliminary © 2007 Microchip Technology Inc.
dsPIC33F 1.0 Note: DEVICE OVERVIEW This data sheet summarizes the features of this group of dsPIC33F devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC30F Family Reference Manual” (DS70046).
dsPIC33F FIGURE 1-1: dsPIC33F GENERAL BLOCK DIAGRAM PSV & Table Data Access Control Block Y Data Bus X Data Bus Interrupt Controller PORTA 16 8 16 16 16 Data Latch Data Latch X RAM Y RAM Address Latch Address Latch DMA RAM 23 PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic 23 23 PORTB DMA 16 16 Controller 16 PORTC Address Generator Units Address Latch Program Memory EA MUX Address Bus Data Latch 24 Instruction Reg Control Signals to Various Blocks Timing Gen
dsPIC33F TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Type Buffer Type AN0-AN31 I Analog AVDD P P Positive supply for analog modules. AVSS P P Ground reference for analog modules. CLKI CLKO I O CN0-CN23 I ST Input change notification inputs. Can be software programmed for internal weak pull-ups on all inputs. COFS CSCK CSDI CSDO I/O I/O I O ST ST ST — Data Converter Interface frame synchronization pin. Data Converter Interface serial clock input/output pin.
dsPIC33F TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Type Buffer Type I/O I/O I/O ST ST ST RB0-RB15 I/O ST PORTB is a bidirectional I/O port. RC1-RC4 RC12-RC15 I/O I/O ST ST PORTC is a bidirectional I/O port. RD0-RD15 I/O ST PORTD is a bidirectional I/O port. RE0-RE9 I/O ST PORTE is a bidirectional I/O port. RF0-RF8 RF12-RF13 I/O ST PORTF is a bidirectional I/O port. RG0-RG3 RG6-RG9 RG12-RG15 I/O I/O I/O ST ST ST PORTG is a bidirectional I/O port.
dsPIC33F 2.0 Note: CPU This data sheet summarizes the features of this group of dsPIC33F devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC30F Family Reference Manual” (DS70046). The dsPIC33F CPU module has a 16-bit (data) modified Harvard architecture with an enhanced instruction set, including significant support for DSP. The CPU has a 24-bit instruction word with a variable length opcode field.
dsPIC33F FIGURE 2-1: dsPIC33F CPU CORE BLOCK DIAGRAM PSV & Table Data Access Control Block Y Data Bus X Data Bus Interrupt Controller 8 16 16 16 16 Data Latch Data Latch X RAM Y RAM Address Latch Address Latch DMA 23 23 PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic RAM 16 23 16 16 DMA Controller Address Generator Units Address Latch Program Memory EA MUX Address Bus Data Latch ROM Latch 24 Control Signals to Various Blocks Instruction Reg Literal Data Instr
dsPIC33F FIGURE 2-2: dsPIC33F PROGRAMMER’S MODEL D15 D0 W0/WREG PUSH.
dsPIC33F 2.
dsPIC33F REGISTER 2-1: SR: CPU STATUS REGISTER (CONTINUED) bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2) 111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8) bit
dsPIC33F REGISTER 2-2: CORCON: CORE CONTROL REGISTER U-0 — bit 15 U-0 — R/W-0 SATA bit 7 R/W-0 SATB bit 11 bit 10-8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: 2: R/W-0 US R/W-0 EDT(1) R-0 R-0 DL<2:0> R-0 bit 8 Legend: R = Readable bit 0’ = Bit is cleared bit 15-13 bit 12 U-0 — R/W-1 SATDW R/W-0 ACCSAT C = Clear only bit W = Writable bit ‘x = Bit is unknown R/C-0 IPL3(2) R/W-0 PSV R/W-0 RND R/W-0 IF bit 0 -n = Value at POR ‘1’ = Bit is set U = Unimplemented bit, re
dsPIC33F 2.5 Arithmetic Logic Unit (ALU) The dsPIC33F ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are 2’s complement in nature. Depending on the operation, the ALU may affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register. The C and DC Status bits operate as Borrow and Digit Borrow bits, respectively, for subtraction operations.
dsPIC33F FIGURE 2-3: DSP ENGINE BLOCK DIAGRAM 40 S a 40 Round t 16 u Logic r a t e 40-bit Accumulator A 40-bit Accumulator B Carry/Borrow Out Saturate Carry/Borrow In Adder Negate 40 40 40 16 X Data Bus Barrel Shifter 40 Y Data Bus Sign-Extend 32 16 Zero Backfill 32 33 17-bit Multiplier/Scaler 16 16 To/From W Array DS70165E-page 34 Preliminary © 2007 Microchip Technology Inc.
dsPIC33F 2.6.1 MULTIPLIER 2.6.2.1 The 17-bit x 17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a scaler to support either 1.31 fractional (Q31) or 32-bit integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed operands are sign-extended into the 17th bit of the multiplier input value. The output of the 17-bit x 17-bit multiplier/scaler is a 33-bit value which is sign-extended to 40 bits.
dsPIC33F The SA and SB bits are modified each time data passes through the adder/subtracter, but can only be cleared by the user. When set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit saturation or bit 39 for 40-bit saturation) and will be saturated (if saturation is enabled). When saturation is not enabled, SA and SB default to bit 39 overflow and, thus, indicate that a catastrophic overflow has occurred.
dsPIC33F 2.6.2.4 Data Space Write Saturation 2.6.3 BARREL SHIFTER In addition to adder/subtracter saturation, writes to data space can also be saturated but without affecting the contents of the source accumulator. The data space write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 16-bit round adder. These inputs are combined and used to select the appropriate 1.
dsPIC33F NOTES: DS70165E-page 38 Preliminary © 2007 Microchip Technology Inc.
dsPIC33F 3.0 MEMORY ORGANIZATION Note: 3.1 This data sheet summarizes the features of this group of dsPIC33F devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC30F Family Reference Manual” (DS70046). The dsPIC33F architecture features separate program and data memory spaces and buses. This architecture also allows the direct access of program memory from the data space during code execution.
dsPIC33F 3.1.1 PROGRAM MEMORY ORGANIZATION 3.1.2 All dsPIC33F devices reserve the addresses between 0x00000 and 0x000200 for hard-coded program execution vectors. A hardware Reset vector is provided to redirect code execution from the default value of the PC on device Reset to the actual start of code. A GOTO instruction is programmed by the user at 0x000000, with the actual address for the start of code at 0x000002. The program memory space is organized in word-addressable blocks.
dsPIC33F 3.2 Data Address Space The dsPIC33F CPU has a separate 16-bit wide data memory space. The data space is accessed using separate Address Generation Units (AGUs) for read and write operations. Data memory maps of devices with different RAM sizes are shown in Figure 3-3 through Figure 3-5. All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to bytes within the data space. This arrangement gives a data space address range of 64 Kbytes or 32K words.
dsPIC33F FIGURE 3-3: DATA MEMORY MAP FOR dsPIC33F DEVICES WITH 8 KBs RAM MSb Address MSb 2-Kbyte SFR Space LSb Address 16 bits LSb 0x0000 0x0001 SFR Space 0x07FE 0x0800 0x07FF 0x0801 8-Kbyte Near Data Space X Data RAM (X) 8-Kbyte SRAM Space 0x17FF 0x1801 0x17FE 0x1800 Y Data RAM (Y) 0x1FFF 0x2001 0x27FF 0x2801 0x1FFE 0x2000 DMA RAM 0x8001 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFF DS70165E-page 42 0x27FE 0x2800 0xFFFE Preliminary © 2007 Microchip Tec
dsPIC33F FIGURE 3-4: DATA MEMORY MAP FOR dsPIC33F DEVICES WITH 16 KBs RAM MSb Address LSb Address 16 bits MSb LSb 0x0000 0x0001 2-Kbyte SFR Space SFR Space 0x07FE 0x0800 0x07FF 0x0801 0x1FFF X Data RAM (X) 0x1FFE 0x27FF 0x2801 16-Kbyte SRAM Space 8-Kbyte Near Data Space 0x27FE 0x2800 Y Data RAM (Y) 0x3FFF 0x4001 0x47FF 0x4801 0x3FFE 0x4000 DMA RAM 0x8001 0x47FE 0x4800 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFE 0xFFFF © 2007 Microchip Technology Inc.
dsPIC33F FIGURE 3-5: DATA MEMORY MAP FOR dsPIC33F DEVICES WITH 30 KBs RAM MSb Address MSb 2-Kbyte SFR Space LSb Address 16 bits LSb 0x0000 0x0001 SFR Space 0x07FE 0x0800 0x07FF 0x0801 8-Kbyte Near Data Space X Data RAM (X) 30-Kbyte SRAM Space 0x47FF 0x4801 0x47FE 0x4800 Y Data RAM (Y) 0x77FF 0x7800 0x7FFF 0x8001 Optionally Mapped into Program Memory DMA RAM X Data Unimplemented (X) 0xFFFF DS70165E-page 44 0x77FE 0x7800 0x7FFE 0x8000 0xFFFE Preliminary © 2007 Microchip Technology Inc.
dsPIC33F 3.2.5 X AND Y DATA SPACES 3.2.6 DMA RAM The core has two data spaces, X and Y. These data spaces can be considered either separate (for some DSP instructions), or as one unified linear address range (for MCU instructions). The data spaces are accessed using two Address Generation Units (AGUs) and separate data paths.
CPU CORE REGISTERS MAP Preliminary SFR Name SFR Addr WREG0 0000 Working Register 0 0000 WREG1 0002 Working Register 1 0000 WREG2 0004 Working Register 2 0000 WREG3 0006 Working Register 3 0000 WREG4 0008 Working Register 4 0000 WREG5 000A Working Register 5 0000 WREG6 000C Working Register 6 0000 WREG7 000E Working Register 7 0000 WREG8 0010 Working Register 8 0000 WREG9 0012 Working Register 9 0000 WREG10 0014 Working Register 10 0000 WREG11 0016 Working Re
© 2007 Microchip Technology Inc.
SFR Name SFR Addr INTERRUPT CONTROLLER REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE INTCON2 0082 ALTIVT DISI — — — IFS0 0084 — DMA1IF AD1IF U1TXIF U1RXIF IFS1 0086 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF — Bit 6 Bit 5 Bit 4 Bit 3 All Resets OSCFAIL — 0000 INT1EP INT0EP 0000 OC1IF IC1IF INT0IF 0000 — MI2C1IF SI2C1IF 0000 0000 Bit 8 OVBTE COVTE — — — — — INT4EP INT3EP INT2EP T3IF T2I
© 2007 Microchip Technology Inc.
Preliminary SFR Name SFR Addr IC1BUF 0140 IC1CON 0142 IC2BUF 0144 IC2CON 0146 IC3BUF 0148 IC3CON 014A IC4BUF 014C IC4CON 014E IC5BUF 0150 IC5CON 0152 IC6BUF 0154 IC6CON 0156 IC7BUF 0158 IC7CON 015A IC8BUF 015C IC8CON 015E Legend: INPUT CAPTURE REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 — — ICSIDL — — — — Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 ICI<1:0> ICOV ICBNE ICM<2:0> ICI<1:0> ICOV ICBNE ICM<2:0> ICI<1:0> ICOV
© 2007 Microchip Technology Inc.
SFR Name Addr.
© 2007 Microchip Technology Inc. TABLE 3-8: SFR Name Addr .
UART1 REGISTER MAP SFR Name SFR Addr U1MODE 0220 UARTEN U1STA 0222 UTXISEL1 U1TXREG 0224 — — U1RXREG 0226 — — U1BRG 0228 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
© 2007 Microchip Technology Inc.
File Name Addr DMA REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 DMA0CON 0380 CHEN SIZE DIR HALF NULLW — — — — — DMA0REQ 0382 FORCE — — — — — — — — Bit 5 Bit 4 AMODE<1:0> Bit 3 Bit 2 — — Bit 1 Bit 0 MODE<1:0> IRQSEL<6:0> All Resets 0000 0000 DMA0STA 0384 STA<15:0> 0000 DMA0STB 0386 STB<15:0> 0000 DMA0PAD 0388 PAD<15:0> DMA0CNT 038A — — — — — — DMA1CON 038C CHEN SIZE DIR HALF NULLW — — — — DMA1REQ 038E
© 2007 Microchip Technology Inc.
File Name ECAN1 REGISTER MAP WHEN C1CTRL1.
© 2007 Microchip Technology Inc. TABLE 3-20: File Name ECAN1 REGISTER MAP WHEN C1CTRL1.
File Name ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1 (CONTINUED) Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 C1RXF11SID 046C SID<10:3> C1RXF11EID 046E EID<15:8> C1RXF12SID 0470 SID<10:3> C1RXF12EID 0472 EID<15:8> C1RXF13SID 0474 SID<10:3> C1RXF13EID 0476 EID<15:8> C1RXF14SID 0478 SID<10:3> C1RXF14EID 047A EID<15:8> C1RXF15SID 047C SID<10:3> C1RXF15EID 047E EID<15:8> Legend: Bit 10 Bit 9 Bit 8 Bit 7 x = unknown value on Reset, — = unimplemented, read as ‘0’.
© 2007 Microchip Technology Inc. TABLE 3-21: File Name ECAN2 REGISTER MAP WHEN C2CTRL1.
File Name Addr ECAN2 REGISTER MAP WHEN C2CTRL1.
© 2007 Microchip Technology Inc. TABLE 3-23: File Name Addr ECAN2 REGISTER MAP WHEN C2CTRL1.
SFR Name DCI REGISTER MAP Addr.
© 2007 Microchip Technology Inc.
PORTG REGISTER MAP(1) Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets TRISG 02E4 TRISG15 TRISG14 TRISG13 TRISG12 — — TRISG9 TRISG8 TRISG7 TRISG6 — — TRISG3 TRISG2 TRISG1 TRISG0 F3CF PORTG 02E6 RG15 RG14 RG13 RG12 — — RG9 RG8 RG7 RG6 — — RG3 RG2 RG1 RG0 xxxx LATG 02E8 LATG15 LATG14 LATG13 LATG12 — — LATG9 LATG8 LATG7 LATG6 — — LATG3 LATG2 LATG1 LATG0 xxxx ODCG 06E
dsPIC33F 3.2.7 SOFTWARE STACK 3.2.8 In addition to its use as a working register, the W15 register in the dsPIC33F devices is also used as a software Stack Pointer. The Stack Pointer always points to the first available free word and grows from lower to higher addresses. It pre-decrements for stack pops and post-increments for stack pushes, as shown in Figure 3-6. For a PC push during any CALL instruction, the MSb of the PC is zero-extended before the push, ensuring that the MSb is always clear.
dsPIC33F TABLE 3-35: FUNDAMENTAL ADDRESSING MODES SUPPORTED Addressing Mode Description File Register Direct The address of the file register is specified explicitly. Register Direct The contents of a register are accessed directly. Register Indirect The contents of Wn forms the EA. Register Indirect Post-Modified The contents of Wn forms the EA. Wn is post-modified (incremented or decremented) by a constant value.
dsPIC33F advisable to use W14 or W15 for Modulo Addressing since these two registers are used as the Stack Frame Pointer and Stack Pointer, respectively. In general, any particular circular buffer can only be configured to operate in one direction as there are certain restrictions on the buffer start address (for incrementing buffers), or end address (for decrementing buffers), based upon the direction of the buffer. The only exception to the usage restrictions is for buffers which have a power-of-2 length.
dsPIC33F 3.4.3 MODULO ADDRESSING APPLICABILITY Modulo Addressing can be applied to the Effective Address (EA) calculation associated with any W register. It is important to realize that the address boundaries check for addresses less than, or greater than, the upper (for incrementing buffers) and lower (for decrementing buffers) boundary addresses (not just equal to). Address changes may, therefore, jump beyond boundaries and still be adjusted correctly. Note: 3.
dsPIC33F FIGURE 3-8: BIT-REVERSED ADDRESS EXAMPLE Sequential Address b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 0 Bit Locations Swapped Left-to-Right Around Center of Binary Value b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1 b2 b3 b4 0 Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-Word Bit-Reversed Buffer TABLE 3-36: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address A3 A2 A1 A0 Bit-Reversed Address Decimal A3 A2 A1 A0 Decimal 0 0 0 0 0 0 0 0 0 0 0 0 0 1
dsPIC33F 3.6 3.6.1 Interfacing Program and Data Memory Spaces Since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is needed to create a 23-bit or 24-bit program address from 16-bit data registers. The solution depends on the interface method to be used. The dsPIC33F architecture uses a 24-bit wide program space and a 16-bit wide data space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the program space.
dsPIC33F FIGURE 3-9: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Program Counter(1) Program Counter 0 0 23 bits EA Table Operations(2) 1/0 1/0 TBLPAG 8 bits 16 bits 24 bits Select Program Space Visibility(1) (Remapping) EA 1 0 PSVPAG 0 8 bits 15 bits 23 bits User/Configuration Space Select Byte Select Note 1: The LSb of program space addresses is always fixed as ‘0’ in order to maintain word alignment of data in the program and data spaces.
dsPIC33F 3.6.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS 2. TBLRDH (Table Read High): In Word mode, it maps the entire upper word of a program address (P<23:16>) to a data address. Note that D<15:8>, the ‘phantom byte’, will always be ‘0’. The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program space without going through data space.
dsPIC33F 3.6.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This option provides transparent access of stored constant data from the data space without the need to use special instructions (i.e., TBLRDL/H).
dsPIC33F NOTES: DS70165E-page 76 Preliminary © 2007 Microchip Technology Inc.
dsPIC33F 4.0 FLASH PROGRAM MEMORY Note: RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user can write program memory data either in blocks or ‘rows’ of 64 instructions (192 bytes) at a time or a single program memory word, and erase program memory in blocks or ‘pages’ of 512 instructions (1536 bytes) at a time. This data sheet summarizes the features of this group of dsPIC33F devices. It is not intended to be a comprehensive reference source.
dsPIC33F 4.2 RTSP Operation 4.3 The dsPIC33F Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user to erase a page of memory, which consists of eight rows (512 instructions) at a time, and to program one row or one word at a time. Table 26-11, DC Characteristics: Program Memory shows typical erase and programming times.
dsPIC33F REGISTER 4-1: NVMCON: FLASH MEMORY CONTROL REGISTER R/SO-0(1) R/W-0(1) R/W-0(1) U-0 U-0 U-0 U-0 U-0 WR WREN WRERR — — — — — bit 15 bit 8 R/W-0(1) U-0 — ERASE U-0 — R/W-0(1) U-0 R/W-0(1) — R/W-0(1) NVMOP<3:0> R/W-0(1) (2) bit 7 bit 0 Legend: SO = Satiable only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 WR: Write Control bit 1 = Initiates a Flash m
dsPIC33F 4.4.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY 4. 5. The user can program one row of program Flash memory at a time. To do this, it is necessary to erase the 8-row erase page that contains the desired row. The general process is: 1. 2. 3. Read eight rows of program memory (512 instructions) and store in data RAM. Update the program data in RAM with the desired new data. Erase the block (see Example 4-1): a) Set the NVMOP bits (NVMCON<3:0>) to ‘0010’ to configure for block erase.
dsPIC33F EXAMPLE 4-2: LOADING THE WRITE BUFFERS ; Set up NVMCON for row programming operations MOV #0x4001, W0 ; MOV W0, NVMCON ; Initialize NVMCON ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled MOV #0x0000, W0 ; MOV W0, TBLPAG ; Initialize PM Page Boundary SFR MOV #0x6000, W0 ; An example program memory address ; Perform the TBLWT instructions to write the latches ; 0th_program_word MOV #LOW_WORD_0, W2 ; MOV #HIGH_BYTE_0, W3 ; TBLWTL W2
dsPIC33F NOTES: DS70165E-page 82 Preliminary © 2007 Microchip Technology Inc.
dsPIC33F 5.0 Note: RESETS Note: This data sheet summarizes the features of this group of dsPIC33F devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC30F Family Reference Manual” (DS70046). The Reset module combines all Reset sources and controls the device Master Reset Signal, SYSRST.
dsPIC33F RCON: RESET CONTROL REGISTER(1) REGISTER 5-1: R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 TRAPR IOPUWR — — — — — VREGS bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 EXTR SWR SWDTEN(2) WDTO SLEEP IDLE BOR POR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TRAPR: Trap Reset Flag bit 1 = A Trap Conflict Reset has occurred 0 =
dsPIC33F RCON: RESET CONTROL REGISTER(1) REGISTER 5-1: bit 0 POR: Power-on Reset Flag bit 1 = A Power-up Reset has occurred 0 = A Power-up Reset has not occurred Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not cause a device Reset. If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting.
dsPIC33F TABLE 5-3: Reset Type POR RESET DELAY TIMES FOR VARIOUS DEVICE RESETS SYSRST Delay System Clock Delay FSCM Delay EC, FRC, LPRC TPOR + TSTARTUP + TRST — — Clock Source Notes 1, 2, 3 ECPLL, FRCPLL TPOR + TSTARTUP + TRST TLOCK TFSCM 1, 2, 3, 5, 6 XT, HS, SOSC TPOR + TSTARTUP + TRST TOST TFSCM 1, 2, 3, 4, 6 XTPLL, HSPLL TPOR + TSTARTUP + TRST TOST + TLOCK TFSCM 1, 2, 3, 4, 5, 6 MCLR Any Clock TRST — — 3 WDT Any Clock TRST — — 3 Software Any Clock TRST — — 3 Il
dsPIC33F 6.0 Note: INTERRUPT CONTROLLER 6.1.1 This data sheet summarizes the features of this group of dsPIC33F devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC30F Family Reference Manual” (DS70046). The dsPIC33F interrupt controller reduces the numerous peripheral interrupt request signals to a single interrupt request signal to the dsPIC33F CPU.
dsPIC33F Decreasing Natural Order Priority FIGURE 6-1: Note 1: DS70165E-page 88 dsPIC33F INTERRUPT VECTOR TABLE Reset – GOTO Instruction Reset – GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector DMA Error Trap Vector Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 ~ ~ ~ Interrupt Vector 52 Interrupt Vector 53 Interrupt Vector 54 ~ ~ ~ Interrupt Vector 116 Interrupt Vector 117 Reserved Reserved Reserved Oscillator Fail Trap
dsPIC33F TABLE 6-1: INTERRUPT VECTORS Vector Number Interrupt Request (IRQ) Number IVT Address AIVT Address 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 0x000014 0x000016 0x000018 0x00001A 0x00001C 0x00001E 0x000020 0x000022 0x000024 0x000026 0x000028 0x00002A 0x00002C 0x00002E 0x0000
dsPIC33F TABLE 6-1: INTERRUPT VECTORS (CONTINUED) Vector Number Interrupt Request (IRQ) Number IVT Address AIVT Address 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 0x000070 0x000072 0x000074 0x000076 0x000078 0x00007A 0x00007C 0x00007E 0x000080 0x000082 0x000084 0x000086 0x000088 0x00008A 0x00008C 0x00008E 0x000090 0x000170 0x000172 0x000174 0x000176 0x000178 0x00017A 0x00017C 0x00017E 0x000180 0x000182 0x000184 0x000186 0x000188 0x00018A 0x
dsPIC33F 6.3 Interrupt Control and Status Registers The IPC registers are used to set the interrupt priority level for each source of interrupt. Each user interrupt source can be assigned to one of eight priority levels. dsPIC33F devices implement a total of 30 registers for the interrupt controller: • • • • • • INTCON1 INTCON2 IFS0 through IFS4 IEC0 through IEC4 IPC0 through IPC17 INTTREG Global interrupt control functions are controlled from INTCON1 and INTCON2.
dsPIC33F REGISTER 6-1: SR: CPU STATUS REGISTER(1) R-0 R-0 R/C-0 R/C-0 R-0 R/C-0 R -0 R/W-0 OA OB SA SB OAB SAB DA DC bit 15 bit 8 R/W-0(3) IPL2 R/W-0(3) (2) IPL1 (2) R/W-0(3) R-0 R/W-0 R/W-0 R/W-0 R/W-0 IPL0(2) RA N OV Z C bit 7 bit 0 Legend: C = Clear only bit R = Readable bit U = Unimplemented bit, read as ‘0’ S = Set only bit W = Writable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown IPL<2:0>: CPU Interrupt Priority Level St
dsPIC33F REGISTER 6-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 SFTACERR DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 NSTDIS: Interrupt Nesting Disable
dsPIC33F REGISTER 6-3: INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED) bit 3 ADDRERR: Address Error Trap Status bit 1 = Address error trap has occurred 0 = Address error trap has not occurred bit 2 STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ DS70165E-page 94 Prelimi
dsPIC33F REGISTER 6-4: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 ALTIVT DISI — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — INT4EP INT3EP INT2EP INT1EP INT0EP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit 1 = Use alternate vector table 0 = Use standard
dsPIC33F REGISTER 6-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T2IF OC2IF IC2IF DMA01IF T1IF OC1IF IC1IF INT0IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’
dsPIC33F REGISTER 6-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED) bit 2 OC1IF: Output Compare Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2007 Microchip Technology In
dsPIC33F REGISTER 6-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA21IF bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IC8IF IC7IF AD2IF INT1IF CNIF — MI2C1IF SI2C1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 U2TXIF: UART2 Transmitter
dsPIC33F REGISTER 6-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 (CONTINUED) bit 3 CNIF: Input Change Notification Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 Unimplemented: Read as ‘0’ bit 1 MI2C1IF: I2C1 Master Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not
dsPIC33F REGISTER 6-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T6IF DMA4IF — OC8IF OC7IF OC6IF OC5IF IC6IF bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IC5IF IC4IF IC3IF DMA3IF C1IF C1RXIF SPI2IF SPI2EIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 T6IF: Timer6 Interrupt Flag St
dsPIC33F REGISTER 6-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2 (CONTINUED) bit 2 C1RXIF: ECAN1 Receive Data Ready Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 SPI2IF: SPI2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SPI2EIF: SPI2 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2007 Microchip Technology Inc.
dsPIC33F REGISTER 6-8: IFS3: INTERRUPT FLAG STATUS REGISTER 3 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTAIF — DMA5IF DCIIF DCIEIF QEIIF PWMIF C2IF bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 C2RXIF INT4IF INT3IF T9IF T8IF MI2C2IF SI2C2IF T7IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FLTAIF: PWM Fault A Interrup
dsPIC33F REGISTER 6-8: IFS3: INTERRUPT FLAG STATUS REGISTER 3 (CONTINUED) bit 2 MI2C2IF: I2C2 Master Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 SI2C2IF: I2C2 Slave Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 T7IF: Timer7 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2007 Microchip Technology Inc.
dsPIC33F REGISTER 6-9: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 C2TXIF C1TXIF DMA7IF DMA6IF — U2EIF U1EIF FLTBIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 C2TXIF: ECAN2 Transmit Data Request Inte
dsPIC33F REGISTER 6-10: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — DMA1IE AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14 DMA1IE: D
dsPIC33F REGISTER 6-10: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) bit 2 OC1IE: Output Compare Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70165E-page 106 Preliminary © 2007 Microchip Technology Inc.
dsPIC33F REGISTER 6-11: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE DMA2IE bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IC8IE IC7IE AD2IE INT1IE CNIE — MI2C1IE SI2C1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 U2TXIE: UART2 Transmitter Interrupt Enable
dsPIC33F REGISTER 6-11: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 (CONTINUED) bit 3 CNIE: Input Change Notification Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 2 Unimplemented: Read as ‘0’ bit 1 MI2C1IE: I2C1 Master Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SI2C1IE: I2C1 Slave Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70165E-page 108 Preliminary
dsPIC33F REGISTER 6-12: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T6IE DMA4IE — OC8IE OC7IE OC6IE OC5IE IC6IE bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IC5IE IC4IE IC3IE DMA3IE C1IE C1RXIE SPI2IE SPI2EIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 T6IE: Timer6 Interrupt Enable bit 1 = Interrup
dsPIC33F REGISTER 6-12: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 (CONTINUED) bit 2 C1RXIE: ECAN1 Receive Data Ready Interrupt Enable bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 SPI2IE: SPI2 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SPI2EIE: SPI2 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70165E-page 110 Preliminary © 2007 Microchip Technology Inc.
dsPIC33F REGISTER 6-13: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTAIE — DMA5IE DCIIE DCIEIE QEIIE PWMIE C2IE bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 C2RXIE INT4IE INT3IE T9IE T8IE MI2C2IE SI2C2IE T7IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 FLTAIE: PWM Fault A Interrupt Enable bit 1 =
dsPIC33F REGISTER 6-13: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 (CONTINUED) bit 2 MI2C2IE: I2C2 Master Events Interrupt Enable bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 SI2C2IE: I2C2 Slave Events Interrupt Enable bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 T7IE: Timer7 Interrupt Enable bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS70165E-page 112 Preliminary © 2007 Microchip Techno
dsPIC33F REGISTER 6-14: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 C2TXIE C1TXIE DMA7IE DMA6IE — U2EIE U1EIE FLTBIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Unimplemented: Read as ‘0’ bit 7 C2TXIE: ECAN2 Transmit Data Request Interrupt Enable bit
dsPIC33F REGISTER 6-15: U-0 IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 R/W-1 — R/W-0 R/W-0 T1IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 OC1IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 IC1IP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 INT0IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T1IP<2:0>: Timer1 Interrupt Priority bits 111 = Interrupt is prior
dsPIC33F REGISTER 6-16: U-0 IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 R/W-1 — R/W-0 R/W-0 T2IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 OC2IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 IC2IP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 DMA0IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 T2IP<2:0>: Timer2 Interrupt Priority bits 111
dsPIC33F REGISTER 6-17: U-0 IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 R/W-1 — R/W-0 R/W-0 U1RXIP<2:0> U-0 R/W-1 — R/W-0 R/W-0 SPI1IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 SPI1EIP<2:0> R/W-0 U-0 — R/W-1 R/W-0 R/W-0 T3IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits 111 = Interr
dsPIC33F REGISTER 6-18: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-1 R/W-0 R/W-0 DMA1IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 AD1IP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 U1TXIP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 DMA1IP<2:0>: DMA Channel 1 Data Transfer Complete
dsPIC33F REGISTER 6-19: U-0 IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 R/W-1 — R/W-0 R/W-0 CNIP<2:0> U-0 U-0 U-0 U-0 — — — — bit 15 bit 8 U-0 R/W-1 — R/W-0 MI2C1IP<2:0> R/W-0 U-0 — R/W-1 R/W-0 R/W-0 SI2C1IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 CNIP<2:0>: Change Notification Interrupt Priority bits 111 = Interrupt is
dsPIC33F REGISTER 6-20: U-0 IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 R/W-1 — R/W-0 R/W-0 IC8IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 IC7IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 AD2IP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 INT1IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 IC8IP<2:0>: Input Capture Channel 8 Interrupt Priority bits 111 =
dsPIC33F REGISTER 6-21: U-0 IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6 R/W-1 — R/W-0 R/W-0 T4IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 OC4IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 OC3IP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 DMA2IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 T4IP<2:0>: Timer4 Interrupt Priority bits 111
dsPIC33F REGISTER 6-22: U-0 IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 R/W-1 — R/W-0 R/W-0 U2TXIP<2:0> U-0 R/W-1 — R/W-0 R/W-0 U2RXIP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 INT2IP<2:0> R/W-0 U-0 — R/W-1 R/W-0 R/W-0 T5IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 U2TXIP<2:0>: UART2 Transmitter Interrupt Priority bits 111 = Inte
dsPIC33F REGISTER 6-23: U-0 IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8 R/W-1 — R/W-0 R/W-0 C1IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 C1RXIP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 SPI2IP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 SPI2EIP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 C1IP<2:0>: ECAN1 Event Interrupt Priority bits 111 = Interrupt
dsPIC33F REGISTER 6-24: U-0 IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9 R/W-1 — R/W-0 R/W-0 IC5IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 IC4IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 IC3IP<2:0> R/W-0 U-0 — R/W-1 R/W-0 R/W-0 DMA3IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 IC5IP<2:0>: Input Capture Channel 5 Interrupt
dsPIC33F REGISTER 6-25: U-0 IPC10: INTERRUPT PRIORITY CONTROL REGISTER 10 R/W-1 — R/W-0 R/W-0 OC7IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 OC6IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 OC5IP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 IC6IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 OC7IP<2:0>: Output Compare Channel 7 Interrupt Priority bits 111
dsPIC33F REGISTER 6-26: U-0 IPC11: INTERRUPT PRIORITY CONTROL REGISTER 11 R/W-1 — R/W-0 R/W-0 T6IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 DMA4IP<2:0> bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-1 R/W-0 R/W-0 OC8IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 T6IP<2:0>: Timer6 Interrupt Priority bits 111 = Inte
dsPIC33F REGISTER 6-27: U-0 IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12 R/W-1 — R/W-0 R/W-0 T8IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 MI2C2IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 SI2C2IP<2:0> R/W-0 U-0 — R/W-1 R/W-0 R/W-0 T7IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T8IP<2:0>: Timer8 Interrupt Priority bits 111 = Interrupt is pr
dsPIC33F REGISTER 6-28: U-0 IPC13: INTERRUPT PRIORITY CONTROL REGISTER 13 R/W-1 — R/W-0 R/W-0 C2RXIP<2:0> U-0 R/W-1 — R/W-0 R/W-0 INT4IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 INT3IP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 T9IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 C2RXIP<2:0>: ECAN2 Receive Data Ready Interrupt Priority bits
dsPIC33F REGISTER 6-29: U-0 IPC14: INTERRUPT PRIORITY CONTROL REGISTER 14 R/W-1 — R/W-0 R/W-0 DCIEIP<2:0> U-0 R/W-1 — R/W-0 R/W-0 QEIIP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 PWMIP<2:0> R/W-0 U-0 — R/W-1 R/W-0 R/W-0 C2IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 DCIEIP<2:0>: DCI Error Interrupt Priority bits 111 = Interrupt is
dsPIC33F REGISTER 6-30: U-0 IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15 R/W-1 R/W-0 — R/W-0 FLTAIP<2:0> U-0 U-0 U-0 U-0 — — — — bit 15 bit 8 U-0 R/W-1 — R/W-0 DMA5IP<2:0> R/W-0 U-0 — R/W-1 R/W-0 R/W-0 DCIIP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 FLTAIP<2:0>: PWM Fault A Interrupt Priority bits 111
dsPIC33F REGISTER 6-31: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-1 R/W-0 R/W-0 U2EIP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 U1EIP<2:0> R/W-0 U-0 — R/W-1 R/W-0 R/W-0 FLTBIP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 U2EIP<2:0>: UART2 Error Interrupt Priority bits 111 = Interrupt is pr
dsPIC33F REGISTER 6-32: U-0 IPC17: INTERRUPT PRIORITY CONTROL REGISTER 17 R/W-1 — R/W-0 R/W-0 C2TXIP<2:0> U-0 R/W-1 — R/W-0 R/W-0 C1TXIP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 DMA7IP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 DMA6IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 C2TXIP<2:0>: ECAN2 Transmit Data Request
dsPIC33F REGISTER 6-33: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER R-0 R/W-0 U-0 U-0 — — — — R-0 R-0 R-0 R-0 ILR<3:0> bit 15 bit 8 U-0 R-0 R-0 R-0 — R-0 R-0 R-0 R-0 VECNUM<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 ILR: New CPU Interrupt Priority Level bits 1111 = CPU Interrupt Priority Level is 15 • • • 0001 = CPU
dsPIC33F 6.4 6.4.3 Interrupt Setup Procedures 6.4.1 INITIALIZATION To configure an interrupt source: 1. 2. Set the NSTDIS bit (INTCON1<15>) if nested interrupts are not desired. Select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate IPCx register. The priority level will depend on the specific application and type of interrupt source.
dsPIC33F NOTES: DS70165E-page 134 Preliminary © 2007 Microchip Technology Inc.
dsPIC33F 7.0 Note: DIRECT MEMORY ACCESS (DMA) The DMA controller features eight identical data transfer channels. This data sheet summarizes the features of this group of dsPIC33F devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC30F Family Reference Manual” (DS70046). Direct Memory Access (DMA) is a very efficient mechanism of copying data between peripheral SFRs (e.g.
dsPIC33F FIGURE 7-1: TOP LEVEL SYSTEM ARCHITECTURE USING A DEDICATED TRANSACTION BUS Peripheral Indirect Address DMA Control DMA Controller DMA RAM SRAM PORT 1 SRAM X-Bus DMA Ready Peripheral 3 DMA Channels PORT 2 CPU DMA DMA DS Bus CPU Peripheral DS Bus CPU CPU Non-DMA Ready Peripheral DMA DMA Ready Peripheral 1 CPU DMA DMA Ready Peripheral 2 Note: CPU and DMA address buses are not shown for clarity. 7.
dsPIC33F write collision (PWCOLx) status bits in a DMAC Status register (DMACS0) to allow the DMAC error trap handler to determine the source of the Fault condition. 7.2.1 BYTE OR WORD TRANSFER Each DMA channel can be configured to transfer words or bytes. As usual, words can only be moved to and from aligned (even) addresses. Bytes can be moved to or from any (legal) address. If the SIZE bit (DMAxCON<14>) is clear, word sized data is transferred.
dsPIC33F 7.2.5 CONTINUOUS OR ONE-SHOT OPERATION Each DMA channel can be configured for One-Shot or Continuous mode operation. If MODE<0> (DMAxCON<0>) is clear, the channel operates in Continuous mode. When all data has been moved (i.e., buffer end has been detected), the channel is automatically reconfigured for subsequent use. During the last data transfer, the next Effective Address generated will be the original start address (from the selected DMAxSTA or DMAxSTB register).
dsPIC33F 7.
dsPIC33F REGISTER 7-1: DMAxCON: DMA CHANNEL x CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 CHEN SIZE DIR HALF NULLW — — — bit 15 bit 8 U-0 U-0 — — R/W-0 R/W-0 AMODE<1:0> U-0 U-0 — — R/W-0 R/W-0 MODE<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CHEN: Channel Enable bit 1 = Channel enabled 0 = Channel disabled bit 14 SIZE
dsPIC33F REGISTER 7-2: DMAxREQ: DMA CHANNEL x IRQ SELECT REGISTER R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 FORCE(1) — — — — — — — bit 15 bit 8 U-0 — R/W-0 IRQSEL6 R/W-0 (2) IRQSEL5 R/W-0 (2) IRQSEL4 U-0 (2) IRQSEL3 U-0 (2) IRQSEL2 R/W-0 (2) IRQSEL1 R/W-0 (2) IRQSEL0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FORCE: Force DMA Transfer bit(1) 1
dsPIC33F REGISTER 7-3: R/W-0 DMAxSTA: DMA CHANNEL x RAM START ADDRESS REGISTER A(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STA<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STA<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 Note 1: x = Bit is unknown STA<15:0>: Primary DMA RAM Start Address bits (source or destination) A read of this address regi
dsPIC33F REGISTER 7-5: R/W-0 DMAxPAD: DMA CHANNEL x PERIPHERAL ADDRESS REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PAD<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PAD<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 Note 1: x = Bit is unknown PAD<15:0>: Peripheral Address Register bits If the channel is enabled (i.e.
dsPIC33F REGISTER 7-7: DMACS0: DMA CONTROLLER STATUS REGISTER 0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 PWCOL7 PWCOL6 PWCOL5 PWCOL4 PWCOL3 PWCOL2 PWCOL1 PWCOL0 bit 15 bit 8 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 XWCOL7 XWCOL6 XWCOL5 XWCOL4 XWCOL3 XWCOL2 XWCOL1 XWCOL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 PWCOL7: Channel 7 Peripheral W
dsPIC33F REGISTER 7-7: DMACS0: DMA CONTROLLER STATUS REGISTER 0 (CONTINUED) bit 3 XWCOL3: Channel 3 DMA RAM Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 2 XWCOL2: Channel 2 DMA RAM Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 1 XWCOL1: Channel 1 DMA RAM Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 0 XWCOL0: Channel 0 DMA RAM Write Collision Flag bit 1 = Write collis
dsPIC33F REGISTER 7-8: DMACS1: DMA CONTROLLER STATUS REGISTER 1 U-0 U-0 U-0 U-0 — — — — R-1 R-1 R-1 R-1 LSTCH<3:0> bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 LSTCH<3:0>: Last DMA Channel Active bits 1111 = No DMA transfer has o
dsPIC33F REGISTER 7-9: R-0 DSADR: MOST RECENT DMA RAM ADDRESS R-0 R-0 R-0 R-0 R-0 R-0 R-0 DSADR<15:8> bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 DSADR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown DSADR<15:0>: Most Recent DMA RAM Address Accessed by DMA Controller bits © 2007 Microchip Technology Inc.
dsPIC33F NOTES: DS70165E-page 148 Preliminary © 2007 Microchip Technology Inc.
dsPIC33F OSCILLATOR CONFIGURATION Note: This data sheet summarizes the features of this group of dsPIC33F devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC30F Family Reference Manual” (DS70046).
dsPIC33F 8.1 CPU Clocking System There are seven system clock options provided by the dsPIC33F: • • • • • • • FRC Oscillator FRC Oscillator with PLL Primary (XT, HS or EC) Oscillator Primary Oscillator with PLL Secondary (LP) Oscillator LPRC Oscillator FRC Oscillator with postscaler 8.1.1 Instruction execution speed or device operating frequency, FCY, is given by: SYSTEM CLOCK SOURCES The primary oscillator can use one of the following as its clock source: 2. 3.
dsPIC33F EQUATION 8-3: For example, suppose a 10 MHz crystal is being used, with “XT with PLL” being the selected oscillator mode. If PLLPRE<4:0> = 0, then N1 = 2. This yields a VCO input of 10/2 = 5 MHz, which is within the acceptable range of 0.8-8 MHz. If PLLDIV<8:0> = 0x1E, then M = 32. This yields a VCO output of 5 x 32 = 160 MHz, which is within the 100-200 MHz ranged needed. FCY = XT WITH PLL MODE EXAMPLE FOSC 1 10000000*32 = = 40 MIPS 2 2 2*2 ( ) If PLLPOST<1:0> = 0, then N2 = 2.
dsPIC33F REGISTER 8-1: U-0 OSCCON: OSCILLATOR CONTROL REGISTER R-0 — R-0 R-0 COSC<2:0> U-0 R/W-y R/W-y — R/W-y NOSC<2:0> bit 15 bit 8 R/W-0 U-0 R-0 U-0 R/C-0 U-0 R/W-0 R/W-0 CLKLOCK — LOCK — CF — LPOSCEN OSWEN bit 7 bit 0 Legend: y = Value set from Configuration bits on POR R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 COSC<
dsPIC33F REGISTER 8-2: R/W-0 CLKDIV: CLOCK DIVISOR REGISTER R/W-0 ROI R/W-0 R/W-0 R/W-0 R/W-1 DOZEN(1) DOZE<2:0> R/W-0 R/W-0 FRCDIV<2:0> bit 15 bit 8 R/W-0 R/W-1 PLLPOST<1:0> U-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 PLLPRE<4:0> bit 7 bit 0 Legend: y = Value set from Configuration bits on POR R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROI: Recover on Interrupt bit 1 = In
dsPIC33F REGISTER 8-3: PLLFBD: PLL FEEDBACK DIVISOR REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0(1) — — — — — — — PLLDIV<8> bit 15 bit 8 R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 PLLDIV<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8-0 PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL mult
dsPIC33F REGISTER 8-4: OSCTUN: FRC OSCILLATOR TUNING REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits 011111 = Center frequency + 11.
dsPIC33F 8.2 Clock Switching Operation Applications are free to switch between any of the four clock sources (Primary, LP, FRC and LPRC) under software control at any time. To limit the possible side effects that could result from this flexibility, dsPIC33F devices have a safeguard lock built into the switch process. Note: 8.2.1 Primary Oscillator mode has three different submodes (XT, HS and EC) which are determined by the POSCMD<1:0> Configuration bits.
dsPIC33F 9.0 Note: POWER-SAVING FEATURES This data sheet summarizes the features of this group of dsPIC33F devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC30F Family Reference Manual” (DS70046). The dsPIC33F devices provide the ability to manage power consumption by selectively managing clocking to the CPU and the peripherals.
dsPIC33F 9.2.2 IDLE MODE Idle mode has these features: • The CPU stops executing instructions. • The WDT is automatically cleared. • The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 9.4 “Peripheral Module Disable”). • If the WDT or FSCM is enabled, the LPRC also remains active.
dsPIC33F 10.0 Note: I/O PORTS This data sheet summarizes the features of this group of dsPIC33F devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC30F Family Reference Manual” (DS70046). All of the device pins (except VDD, VSS, MCLR and OSC1/CLKIN) are shared between the peripherals and the parallel I/O ports. All I/O input ports feature Schmitt Trigger inputs for improved noise immunity. 10.
dsPIC33F 10.2 Open-Drain Configuration 10.4 In addition to the PORT, LAT and TRIS registers for data control, each port pin can also be individually configured for either digital or open-drain output. This is controlled by the Open-Drain Control register, ODCx, associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain output. The open-drain feature allows the generation of outputs higher than VDD (e.g.
dsPIC33F 11.0 Note: TIMER1 Figure 11-1 presents a block diagram of the 16-bit timer module. This data sheet summarizes the features of this group of dsPIC33F devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC30F Family Reference Manual” (DS70046). To configure Timer1 for operation: 1. 2. 3.
dsPIC33F REGISTER 11-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 — TGATE R/W-0 R/W-0 TCKPS<1:0> U-0 R/W-0 R/W-0 U-0 — TSYNC TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 bit 14 Unimplemented: Read as ‘0’ bit 13 TS
dsPIC33F 12.0 Note: TIMER2/3, TIMER4/5, TIMER6/7 AND TIMER8/9 This data sheet summarizes the features of this group of dsPIC33F devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC30F Family Reference Manual” (DS70046). The Timer2/3, Timer4/5, Timer6/7 and Timer8/9 modules are 32-bit timers, which can also be configured as four independent 16-bit timers with selectable operating modes.
dsPIC33F TIMER2/3 (32-BIT) BLOCK DIAGRAM(1) FIGURE 12-1: T2CK 1x Gate Sync 01 TCY 00 TCKPS<1:0> 2 TON Prescaler 1, 8, 64, 256 TGATE TCS TGATE Q 1 Set T3IF Q D CK 0 PR2 PR3 ADC Event Trigger(2) Equal Comparator MSb LSb TMR3 Reset TMR2 Sync 16 Read TMR2 Write TMR2 16 16 TMR3HLD 16 Data Bus<15:0> Note 1: 2: The 32-bit timer control bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON register.
dsPIC33F FIGURE 12-2: TIMER2 (16-BIT) BLOCK DIAGRAM TON T2CK TCKPS<1:0> 2 1x Gate Sync Prescaler 1, 8, 64, 256 01 00 TGATE TCS TCY 1 Set T2IF Q D Q CK TGATE 0 Reset Sync TMR2 Comparator Equal PR2 © 2007 Microchip Technology Inc.
dsPIC33F REGISTER 12-1: TxCON (T2CON, T4CON, T6CON OR T8CON) CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 — TGATE R/W-0 R/W-0 TCKPS<1:0> R/W-0 T32 (1) U-0 R/W-0 U-0 — TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timerx On bit When T32 = 1: 1 = Starts 32-bit Timerx/y 0 = Stops 32-bit Timerx/y When
dsPIC33F REGISTER 12-2: TyCON (T3CON, T5CON, T7CON OR T9CON) CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON(1) — TSIDL(1) — — — — — bit 15 bit 8 U-0 R/W-0 — TGATE(1) R/W-0 R/W-0 TCKPS<1:0>(1) U-0 U-0 R/W-0 U-0 — — TCS(1) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timery On bit(1) 1 = Starts 16-bit Timery 0 = Stops 16-bit Timery bit 14 Uni
dsPIC33F NOTES: DS70165E-page 168 Preliminary © 2007 Microchip Technology Inc.
dsPIC33F 13.0 INPUT CAPTURE Note: This data sheet summarizes the features of this group of dsPIC33F devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC30F Family Reference Manual” (DS70046). The input capture module is useful in applications requiring frequency (period) and pulse measurement. The dsPIC33F devices support up to eight input capture channels.
dsPIC33F 13.
dsPIC33F 14.0 Note: 14.1 OUTPUT COMPARE This data sheet summarizes the features of this group of dsPIC33F devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC30F Family Reference Manual” (DS70046). Setup for Single Output Pulse Generation When the OCM control bits (OCxCON<2:0>) are set to ‘100’, the selected output compare channel initializes the OCx pin to the low state and generates a single output pulse.
dsPIC33F 14.3 EQUATION 14-1: Pulse-Width Modulation Mode The following steps should be taken when configuring the output compare module for PWM operation: 1. Set the PWM period by writing to the selected Timer Period register (PRy). Set the PWM duty cycle by writing to the OCxRS register. Write the OxCR register with the initial duty cycle. Enable interrupts, if required, for the timer and output compare modules. The output compare interrupt is required for PWM Fault pin utilization.
dsPIC33F TABLE 14-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 4 MIPS (FCY = 4 MHz) PWM Frequency 7.6 Hz 61 Hz 122 Hz 977 Hz 3.9 kHz 31.3 kHz 125 kHz Timer Prescaler Ratio 8 1 1 1 1 1 1 Period Register Value FFFFh FFFFh 7FFFh 0FFFh 03FFh 007Fh 001Fh 16 16 15 12 10 7 5 Resolution (bits) TABLE 14-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 16 MIPS (FCY = 16 MHz) PWM Frequency 30.5 Hz 244 Hz 488 Hz 3.9 kHz 15.
dsPIC33F 14.
dsPIC33F 15.0 Note: MOTOR CONTROL PWM MODULE This data sheet summarizes the features of this group of dsPIC33F devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC30F Family Reference Manual” (DS70046). This module simplifies the task of generating multiple, synchronized Pulse-Width Modulated (PWM) outputs.
dsPIC33F FIGURE 15-1: PWM MODULE BLOCK DIAGRAM PWMCON1 PWM Enable and Mode SFRs PWMCON2 DTCON1 Dead-Time Control SFRs DTCON2 FLTACON Fault Pin Control SFRs FLTBCON OVDCON PWM Manual Control SFR PWM Generator #4 16-bit Data Bus PDC4 Buffer PDC4 Comparator PWM Generator #3 PTMR Channel 4 Dead-Time Generator and Override Logic PWM4H Channel 3 Dead-Time Generator and Override Logic PWM3H PWM4L Output PWM3L Driver Comparator PWM Generator #2 Channel 2 Dead-Time Generator and Override Logic P
dsPIC33F 15.1 15.1.1 PWM Time Base The PWM time base is provided by a 15-bit timer with a prescaler and postscaler. The time base is accessible via the PTMR SFR. PTMR<15> is a read-only status bit, PTDIR, that indicates the present count direction of the PWM time base. If PTDIR is cleared, PTMR is counting upwards. If PTDIR is set, PTMR is counting downwards. The PWM time base is configured via the PTCON SFR. The time base is enabled/disabled by setting/clearing the PTEN bit in the PTCON SFR.
dsPIC33F 15.1.4 DOUBLE UPDATE MODE In the Double Update mode (PTMOD<1:0> = 11), an interrupt event is generated each time the PTMR register is equal to zero, as well as each time a period match occurs. The postscaler selection bits have no effect in this mode of the timer. The Double Update mode provides two additional functions to the user. First, the control loop bandwidth is doubled because the PWM duty cycles can be updated, twice per period.
dsPIC33F 15.4 15.5.1 Center-Aligned PWM Center-aligned PWM signals are produced by the module when the PWM time base is configured in an Up/Down Count mode (see Figure 15-3). The PWM compare output is driven to the active state when the value of the Duty Cycle register matches the value of PTMR and the PWM time base is counting downwards (PTDIR = 1).
dsPIC33F 15.6 Complementary PWM Operation In the Complementary mode of operation, each pair of PWM outputs is obtained by a complementary PWM signal. A dead time may be optionally inserted during device switching, when both outputs are inactive for a short period (refer to Section 15.7 “Dead-Time Generators”).
dsPIC33F 15.7.2 DEAD-TIME ASSIGNMENT 15.8 The DTCON2 SFR contains control bits that allow the dead times to be assigned to each of the complementary outputs. Table 15-1 summarizes the function of each dead-time selection control bit. TABLE 15-1: Bit DEAD-TIME SELECTION BITS Function DTS1A Selects PWM1L/PWM1H active edge dead time. DTS1I Selects PWM1L/PWM1H inactive edge dead time. DTS2A Selects PWM2L/PWM2H active edge dead time. DTS2I Selects PWM2L/PWM2H inactive edge dead time.
dsPIC33F 15.10.2 OVERRIDE SYNCHRONIZATION 15.12.1 If the OSYNC bit in the PWMCON2 register is set, all output overrides performed via the OVDCON register are synchronized to the PWM time base. Synchronous output overrides occur at the following times: • Edge-Aligned mode – when PTMR is zero • Center-Aligned modes – when PTMR is zero and the value of PTMR matches PTPER 15.
dsPIC33F 15.12.4 FAULT INPUT MODES 15.14 PWM Special Event Trigger Each of the Fault input pins have two modes of operation: • Latched Mode: When the Fault pin is driven low, the PWM outputs will go to the states defined in the FLTACON/FLTBCON registers. The PWM outputs will remain in this state until the Fault pin is driven high and the corresponding interrupt flag has been cleared in software.
dsPIC33F REGISTER 15-1: PTCON: PWM TIME BASE CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 PTEN — PTSIDL — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTOPS<3:0> R/W-0 R/W-0 PTCKPS<1:0> R/W-0 PTMOD<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PTEN: PWM Time Base Timer Enable bit 1 = PWM time base is on 0 = PWM time base is o
dsPIC33F REGISTER 15-2: R-0 PTMR: PWM TIMER COUNT VALUE REGISTER R/W-0 R/W-0 R/W-0 PTDIR R/W-0 R/W-0 R/W-0 R/W-0 PTMR<14:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTMR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PTDIR: PWM Time Base Count Direction Status bit (read-only) 1 = PWM time base is counting down 0 = PWM time base is
dsPIC33F REGISTER 15-4: R/W-0 SEVTCMP: SPECIAL EVENT COMPARE REGISTER R/W-0 R/W-0 R/W-0 SEVTDIR(1) R/W-0 R/W-0 R/W-0 R/W-0 SEVTCMP<14:8>(2) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SEVTCMP<7:0>(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 SEVTDIR: Special Event Trigger Time Base Direction bit(1) 1 = A Special Event Trigger will occ
dsPIC33F REGISTER 15-5: PWMCON1: PWM CONTROL REGISTER 1 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — PMOD4 PMOD3 PMOD2 PMOD1 bit 15 bit 8 R/W-1 R/W-1 (1) (1) PEN3H PEN4H R/W-1 PEN2H (1) R/W-1 (1) PEN1H R/W-1 PEN4L (1) R/W-1 PEN3L (1) R/W-1 PEN2L (1) R/W-1 PEN1L(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 PMOD<
dsPIC33F REGISTER 15-6: PWMCON2: PWM CONTROL REGISTER 2 U-0 U-0 U-0 U-0 — — — — R/W-0 R/W-0 R/W-0 R/W-0 SEVOPS<3:0> bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — IUE OSYNC UDIS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 SEVOPS<3:0>: PWM Special Event Trigger Output Postscale Select bi
dsPIC33F REGISTER 15-7: R/W-0 DTCON1: DEAD-TIME CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 DTBPS<1:0> R/W-0 R/W-0 R/W-0 DTB<5:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DTAPS<1:0> R/W-0 R/W-0 R/W-0 DTA<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 DTBPS<1:0>: Dead-Time Unit B Prescale Select bits 11 = Clock period for Dead-Time Unit B is 8 TCY 10 = Clock period
dsPIC33F REGISTER 15-8: DTCON2: DEAD-TIME CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DTS4A DTS4I DTS3A DTS3I DTS2A DTS2I DTS1A DTS1I bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Unimplemented: Read as ‘0’ bit 7 DTS4A: Dead-Time Select for PWM4 Signal Going Active bit 1 =
dsPIC33F REGISTER 15-9: FLTACON: FAULT A CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FAOV4H FAOV4L FAOV3H FAOV3L FAOV2H FAOV2L FAOV1H FAOV1L bit 15 bit 8 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTAM — — — FAEN4 FAEN3 FAEN2 FAEN1 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 FAOVxH<4:1>:FAOVxL<4:1>: Fault Input A P
dsPIC33F REGISTER 15-10: FLTBCON: FAULT B CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FBOV4H FBOV4L FBOV3H FBOV3L FBOV2H FBOV2L FBOV1H FBOV1L bit 15 bit 8 R/W-0 U-0 — FLTBM U-0 — U-0 R/W-0 R/W-0 R/W-0 R/W-0 — FBEN4(1) FBEN3(1) FBEN2(1) FBEN1(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 FBOVxH<4:1>:FBOVxL<4:1>: Fault
dsPIC33F REGISTER 15-11: OVDCON: OVERRIDE CONTROL REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 POVD4H POVD4L POVD3H POVD3L POVD2H POVD2L POVD1H POVD1L bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 POUT4H POUT4L POUT3H POUT3L POUT2H POUT2L POUT1H POUT1L bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 POVDxH<4:1>:POV
dsPIC33F REGISTER 15-12: PDC1: PWM DUTY CYCLE REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PDC1<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PDC1<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown PDC1<15:0>: PWM Duty Cycle #1 Value bits REGISTER 15-13: PDC2: PWM DUTY CYCLE REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
dsPIC33F REGISTER 15-14: PDC3: PWM DUTY CYCLE REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PDC3<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PDC3<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown PDC3<15:0>: PWM Duty Cycle #3 Value bits REGISTER 15-15: PDC4: PWM DUTY CYCLE REGISTER 4 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
dsPIC33F NOTES: DS70165E-page 196 Preliminary © 2007 Microchip Technology Inc.
dsPIC33F 16.0 QUADRATURE ENCODER INTERFACE (QEI) MODULE Note: The operational features of the QEI include: • Three input channels for two phase signals and index pulse • 16-bit up/down position counter • Count direction status • Position Measurement (x2 and x4) mode • Programmable digital noise filters on inputs • Alternate 16-bit Timer/Counter mode • Quadrature Encoder Interface interrupts This data sheet summarizes the features of this group of dsPIC33F devices.
dsPIC33F 16.1 Quadrature Encoder Interface Logic A typical incremental (a.k.a. optical) encoder has three outputs: Phase A, Phase B and an index pulse. These signals are useful and often required in position and speed control of ACIM and SR motors. The two channels, Phase A (QEA) and Phase B (QEB), have a unique relationship. If Phase A leads Phase B, then the direction (of the motor) is deemed positive or forward. If Phase A lags Phase B, then the direction (of the motor) is deemed negative or reverse.
dsPIC33F 16.4 Programmable Digital Noise Filters The digital noise filter section is responsible for rejecting noise on the incoming capture or quadrature signals. Schmitt Trigger inputs and a 3-clock cycle delay filter combine to reject low-level noise and large, short duration noise spikes that typically occur in noise prone applications, such as a motor system.
dsPIC33F 16.7.2 TIMER OPERATION DURING CPU IDLE MODE When the CPU is placed in the Idle mode and the QEI module is configured in the 16-bit Timer mode, the 16-bit timer will operate if QEISIDL (QEICON<13>) = 0. This bit defaults to a logic ‘0’ upon executing POR. For halting the timer module during the CPU Idle mode, QEISIDL should be set to ‘1’. If the QEISIDL bit is cleared, the timer will function normally as if the CPU Idle mode had not been entered. 16.
dsPIC33F REGISTER 16-1: QEICON: QEI CONTROL REGISTER R/W-0 U-0 R/W-0 R-0 R/W-0 CNTERR — QEISIDL INDEX UPDN R/W-0 R/W-0 R/W-0 QEIM<2:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 SWPAB PCDOUT TQGATE R/W-0 R/W-0 TQCKPS<1:0> R/W-0 R/W-0 R/W-0 POSRES TQCS UPDN_SRC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CNTERR: Count Error Status Flag bit 1 = Position
dsPIC33F REGISTER 16-1: QEICON: QEI CONTROL REGISTER (CONTINUED) bit 4-3 TQCKPS<1:0>: Timer Input Clock Prescale Select bits 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value (Prescaler utilized for 16-bit Timer mode only) bit 2 POSRES: Position Counter Reset Enable bit 1 = Index Pulse resets Position Counter 0 = Index Pulse does not reset Position Counter (Bit only applies when QEIM<2:0> = 100 or 110) bit 1 TQCS: Timer Clock Source Select bit 1 = Exte
dsPIC33F REGISTER 16-2: DFLTCON: DIGITAL FILTER CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0 R/W-0 R/W-0 IMV<2:0> CEID bit 15 bit 8 R/W-0 R/W-0 U-0 U-0 U-0 U-0 QEOUT QECK<2:0> — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-9 IMV<1:0>: Index Match Value bits – These bits allow the user to spe
dsPIC33F NOTES: DS70165E-page 204 Preliminary © 2007 Microchip Technology Inc.
dsPIC33F 17.0 Note: SERIAL PERIPHERAL INTERFACE (SPI) buffer are moved to SPIxSR. The received data is thus placed in SPIxBUF and the transmit data in SPIxSR is ready for the next transfer. This data sheet summarizes the features of this group of dsPIC33F devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC30F Family Reference Manual” (DS70046).
dsPIC33F FIGURE 17-1: SPI MODULE BLOCK DIAGRAM SCKx 1:1 to 1:8 Secondary Prescaler 1:1/4/16/64 Primary Prescaler FCY SSx Sync Control Select Edge Control Clock SPIxCON1<1:0> Shift Control SPIxCON1<4:2> SDOx Enable Master Clock bit 0 SDIx SPIxSR Transfer Transfer SPIxRXB SPIxTXB SPIxBUF Read SPIxBUF Write SPIxBUF 16 Internal Data Bus DS70165E-page 206 Preliminary © 2007 Microchip Technology Inc.
dsPIC33F FIGURE 17-2: SPI MASTER/SLAVE CONNECTION PROCESSOR 1 (SPI Master) PROCESSOR 2 (SPI Slave) SDOx SDIx Serial Receive Buffer (SPIxRXB) Serial Receive Buffer (SPIxRXB) SDIx Shift Register (SPIxSR) SDOx LSb MSb MSb LSb Serial Transmit Buffer (SPIxTXB) Serial Transmit Buffer (SPIxTXB) SPI Buffer (SPIxBUF)(2) Shift Register (SPIxSR) Serial Clock SCKx SCKx SPI Buffer (SPIxBUF)(2) SSx(1) (MSTEN (SPIxCON1<5>) = 1) Note (SSEN (SPIxCON1<7>) = 1 and MSTEN (SPIxCON1<5>) = 0) 1:Using the S
dsPIC33F FIGURE 17-5: SPI SLAVE, FRAME MASTER CONNECTION DIAGRAM PROCESSOR 2 dsPIC33F (SPI Slave, Frame Slave) SDIx SDOx SDOx SDIx Serial Clock SCKx SCKx SSx SSx Frame Sync Pulse FIGURE 17-6: SPI SLAVE, FRAME SLAVE CONNECTION DIAGRAM PROCESSOR 2 dsPIC33F (SPI Master, Frame Slave) SDIx SDOx SDOx SDIx Serial Clock SCKx SCKx SSx SSx Frame Sync Pulse EQUATION 17-1: RELATIONSHIP BETWEEN DEVICE AND SPI CLOCK SPEED FSCK = TABLE 17-1: FCY Primary Prescaler * Secondary Prescaler SAMPLE SCKx FREQ
dsPIC33F REGISTER 17-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 SPIEN — SPISIDL — — — — — bit 15 bit 8 U-0 R/C-0 U-0 U-0 U-0 U-0 R-0 R-0 — SPIROV — — — — SPITBF SPIRBF bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 SPIEN: SPIx Enable bit 1 = Enables module and configures SCKx, SDOx,
dsPIC33F REGISTER 17-2: SPIXCON1: SPIx CONTROL REGISTER 1 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — DISSCK DISSDO MODE16 SMP CKE(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 SSEN CKP MSTEN R/W-0 R/W-0 R/W-0 R/W-0 SPRE<2:0> R/W-0 PPRE<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12 DISSCK: Disable SCKx pin
dsPIC33F REGISTER 17-3: SPIxCON2: SPIx CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 FRMEN SPIFSD FRMPOL — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 — — — — — — FRMDLY — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FRMEN: Framed SPIx Support bit 1 = Framed SPIx support enabled (SSx pin used as frame sync pulse inpu
dsPIC33F NOTES: DS70165E-page 212 Preliminary © 2007 Microchip Technology Inc.
dsPIC33F 18.0 Note: INTER-INTEGRATED CIRCUIT (I2C) This data sheet summarizes the features of this group of dsPIC33F devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC30F Family Reference Manual” (DS70046). The Inter-Integrated Circuit (I2C) module provides complete hardware support for both Slave and MultiMaster modes of the I2C serial communication standard, with a 16-bit interface.
dsPIC33F FIGURE 18-1: I2C™ BLOCK DIAGRAM (X = 1 OR 2) Internal Data Bus I2CxRCV Read SCLx Shift Clock I2CxRSR LSb SDAx Address Match Match Detect Write I2CxMSK Write Read I2CxADD Read Start and Stop Bit Detect Write Start and Stop Bit Generation Control Logic I2CxSTAT Collision Detect Read Write I2CxCON Acknowledge Generation Read Clock Stretching Write I2CxTRN LSb Read Shift Clock Reload Control Write BRG Down Counter I2CxBRG Read TCY/2 DS70165E-page 214 Preliminary © 2007 Microc
dsPIC33F 18.5 I2C Module Addresses 18.8 The I2CxADD register contains the Slave mode addresses. The register is a 10-bit register. If the A10M bit (I2CxCON<10>) is ‘0’, the address is interpreted by the module as a 7-bit address. When an address is received, it is compared to the 7 Least Significant bits of the I2CxADD register. If the A10M bit is ‘1’, the address is assumed to be a 10-bit address.
dsPIC33F 18.11 Slope Control 2 The I C standard requires slope control on the SDAx and SCLx signals for Fast mode (400 kHz). The control bit, DISSLW, enables the user to disable slew rate control if desired. It is necessary to disable the slew rate control for 1 MHz mode. 18.12 Clock Arbitration Clock arbitration occurs when the master deasserts the SCLx pin (SCLx allowed to float high) during any receive, transmit or Restart/Stop condition.
dsPIC33F REGISTER 18-1: I2CxCON: I2Cx CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-1 HC R/W-0 R/W-0 R/W-0 R/W-0 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 HC R/W-0 HC R/W-0 HC R/W-0 HC R/W-0 HC GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HS = Set in hardware HC = Cleared in hardware -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bi
dsPIC33F REGISTER 18-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED) bit 5 ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive) Value that will be transmitted when the software initiates an Acknowledge sequence.
dsPIC33F REGISTER 18-2: I2CxSTAT: I2Cx STATUS REGISTER R-0 HSC R-0 HSC U-0 U-0 U-0 R/C-0 HS R-0 HSC R-0 HSC ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 bit 15 bit 8 R/C-0 HS R/C-0 HS R-0 HSC R/C-0 HSC R/C-0 HSC R-0 HSC R-0 HSC R-0 HSC IWCOL I2COV D_A P S R_W RBF TBF bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HS = Set in hardware HSC = Hardware set/cleared -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is
dsPIC33F REGISTER 18-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. bit 2 R_W: Read/Write Information bit (when operating as I2C slave) 1 = Read – indicates data transfer is output from slave 0 = Write – indicates data transfer is input to slave Hardware set or clear after reception of I 2C device address byte.
dsPIC33F REGISTER 18-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — AMSK9 AMSK8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 AMSK7 AMSK6 AMSK5 AMSK4 AMSK3 AMSK2 AMSK1 AMSK0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9-0 AMSKx: Mask for
dsPIC33F NOTES: DS70165E-page 222 Preliminary © 2007 Microchip Technology Inc.
dsPIC33F 19.0 Note: UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) This data sheet summarizes the features of this group of dsPIC33F devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC30F Family Reference Manual” (DS70046). The Universal Asynchronous Receiver Transmitter (UART) module is one of the serial I/O modules available in the dsPIC33F device family.
dsPIC33F 19.1 UART Baud Rate Generator (BRG) The UART module includes a dedicated 16-bit Baud Rate Generator. The BRGx register controls the period of a free-running 16-bit timer. Equation 19-1 shows the formula for computation of the baud rate with BRGH = 0. Equation 19-2 shows the formula for computation of the baud rate with BRGH = 1.
dsPIC33F 19.2 1. 2. 3. 4. 5. 6. 2. 3. 4. 5. 6. 19.5 Set up the UART: a) Write appropriate values for data, parity and Stop bits. b) Write appropriate baud rate value to the BRGx register. c) Set up transmit and receive interrupt enable and priority bits. Enable the UART. Set the UTXEN bit (causes a transmit interrupt). Write data byte to lower byte of UxTXREG word.
dsPIC33F REGISTER 19-1: UxMODE: UARTx MODE REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 UARTEN — USIDL IREN(1) RTSMD — R/W-0(2) R/W-0(2) UEN<1:0> bit 15 bit 8 R/W-0 HC R/W-0 R/W-0 HC R/W-0 R/W-0 WAKE LPBACK ABAUD URXINV BRGH R/W-0 R/W-0 PDSEL<1:0> R/W-0 STSEL bit 7 bit 0 Legend: HC = Hardware cleared R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 UARTEN: UARTx Enab
dsPIC33F REGISTER 19-1: UxMODE: UARTx MODE REGISTER (CONTINUED) bit 3 BRGH: High Baud Rate Enable bit 1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode) 0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode) bit 2-1 PDSEL<1:0>: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit Note 1: 2: This fe
dsPIC33F REGISTER 19-2: UxSTA: UARTx STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 U-0 R/W-0 HC R/W-0 R-0 R-1 UTXISEL1 UTXINV(1) UTXISEL0 — UTXBRK UTXEN UTXBF TRMT bit 15 bit 8 R/W-0 R/W-0 URXISEL<1:0> R/W-0 R-1 R-0 R-0 R/C-0 R-0 ADDEN RIDLE PERR FERR OERR URXDA bit 7 bit 0 Legend: HC = Hardware cleared R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15,13 UTXISE
dsPIC33F REGISTER 19-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) bit 4 RIDLE: Receiver Idle bit (read-only) 1 = Receiver is Idle 0 = Receiver is active bit 3 PERR: Parity Error Status bit (read-only) 1 = Parity error has been detected for the current character (character at the top of the receive FIFO) 0 = Parity error has not been detected bit 2 FERR: Framing Error Status bit (read-only) 1 = Framing error has been detected for the current character (character at the top of the receive FI
dsPIC33F NOTES: DS70165E-page 230 Preliminary © 2007 Microchip Technology Inc.
dsPIC33F 20.0 Note: ENHANCED CAN MODULE This data sheet summarizes the features of this group of dsPIC33F devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC30F Family Reference Manual” (DS70046). messages on the CAN bus. Messages are transmitted by first loading the appropriate data registers. Status and errors can be checked by reading the appropriate registers.
dsPIC33F FIGURE 20-1: ECAN™ MODULE BLOCK DIAGRAM RXF15 Filter RXF14 Filter RXF13 Filter RXF12 Filter DMA Controller RXF11 Filter RXF10 Filter RXF9 Filter RXF8 Filter TRB7 TX/RX Buffer Control Register RXF7 Filter TRB6 TX/RX Buffer Control Register RXF6 Filter TRB5 TX/RX Buffer Control Register RXF5 Filter TRB4 TX/RX Buffer Control Register RXF4 Filter TRB3 TX/RX Buffer Control Register RXF3 Filter TRB2 TX/RX Buffer Control Register RXF2 Filter RXM2 Mask TRB1 TX/RX Buffer Control Register R
dsPIC33F 20.3 Modes of Operation Note: The CAN module can operate in one of several operation modes selected by the user. These modes include: • • • • • • Initialization Mode Disable Mode Normal Operation Mode Listen Only Mode Listen All Messages Mode Loopback Mode Modes are requested by setting the REQOP<2:0> bits (CiCTRL1<10:8>). Entry into a mode is Acknowledged by monitoring the OPMODE<2:0> bits (CiCTRL1<7:5>).
dsPIC33F An additional buffer is always committed to monitoring the bus for incoming messages. This buffer is called the Message Assembly Buffer (MAB). All messages are assembled by the MAB and are transferred to the buffers only if the acceptance filter criterion are met. When a message is received, the RBIF flag (CiINTF<1>) will be set. The user would then need to inspect the CiVEC and/or CiRXFUL1 register to determine which filter and buffer caused the interrupt to get generated.
dsPIC33F 20.5 20.5.1 20.5.4 Message Transmission TRANSMIT BUFFERS The CAN module has up to eight transmit buffers, located in DMA RAM. These 8 buffers need to be configured as transmit buffers by setting the corresponding TX/RX buffer selection (TXENn or TXENm) bit in a CiTRmnCON register. The overall size of the CAN buffer area in DMA RAM is selectable by the user and is defined by the DMABS<2:0> bits (CiFCTRL<15:13>). Each transmit buffer occupies 16 bytes of data.
dsPIC33F 20.5.7 TRANSMIT INTERRUPTS 20.6 Baud Rate Setting Transmit interrupts can be divided into 2 major groups, each including various conditions that generate interrupts: All nodes on any particular CAN bus must have the same nominal bit rate. In order to set the baud rate, the following parameters have to be initialized: • Transmit Interrupt: At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message for transmission.
dsPIC33F 20.6.2 PRESCALER SETTING There is a programmable prescaler with integral values ranging from 1 to 64, in addition to a fixed divide-by-2 for clock generation. The time quantum (TQ) is a fixed unit of time derived from the oscillator period and is given by Equation 20-1. Note: FCAN must not exceed 40 MHz. If CANCKS = 0, then FCY must not exceed 20 MHz.
dsPIC33F REGISTER 20-1: CiCTRL1: ECAN CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 — — CSIDL ABAT CANCKS R/W-1 R/W-0 R/W-0 REQOP<2:0> bit 15 bit 8 R-1 R-0 R-0 OPMODE<2:0> U-0 R/W-0 U-0 U-0 R/W-0 — CANCAP — — WIN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 CSIDL: Stop in Idle Mode bit 1 = Discontinue mod
dsPIC33F REGISTER 20-2: CiCTRL2: ECAN CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 — — — R-0 R-0 R-0 R-0 R-0 DNCNT<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 DNCNT<4:0>: DeviceNet™ Filter Bit Number bits 10010-11111 = Invalid selection 10001 = Compare up to data byte 3,
dsPIC33F REGISTER 20-3: CiVEC: ECAN INTERRUPT CODE REGISTER U-0 U-0 U-0 — — — R-0 R-0 R-0 R-0 R-0 FILHIT<4:0> bit 15 bit 8 U-0 R-1 R-0 R-0 — R-0 R-0 R-0 R-0 ICODE<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 FILHIT<4:0>: Filter Hit Number bits 10000-11111 = Reserved 01111 = Filter 15 ....
dsPIC33F REGISTER 20-4: R/W-0 CiFCTRL: ECAN FIFO CONTROL REGISTER R/W-0 R/W-0 DMABS<2:0> U-0 U-0 U-0 U-0 U-0 — — — — — bit 15 bit 8 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FSA<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-13 DMABS<2:0>: DMA Buffer Size bits 111 = Reserved 110 = 32 buffers in DMA RAM 101 = 24 buffers in DMA RAM 100 = 16 buffers in DMA RAM
dsPIC33F REGISTER 20-5: CiFIFO: ECAN FIFO STATUS REGISTER U-0 U-0 — — R-0 R-0 R-0 R-0 R-0 R-0 FBP<5:0> bit 15 bit 8 U-0 U-0 — — R-0 R-0 R-0 R-0 R-0 R-0 FNRB<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 FBP<5:0>: FIFO Write Buffer Pointer bits 011111 = RB31 buffer 011110 = RB30 buffer ....
dsPIC33F REGISTER 20-6: CiINTF: ECAN INTERRUPT FLAG REGISTER U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0 — — TXBO TXBP RXBP TXWAR RXWAR EWARN bit 15 bit 8 R/C-0 R/C-0 R/C-0 U-0 R/C-0 R/C-0 R/C-0 R/C-0 IVRIF WAKIF ERRIF — FIFOIF RBOVIF RBIF TBIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 TXBO: Transmitter in Er
dsPIC33F REGISTER 20-7: CiINTE: ECAN INTERRUPT ENABLE REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IVRIE WAKIE ERRIE — FIFOIE RBOVIE RBIE TBIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Unimplemented: Read as ‘0’ bit 7 IVRIE: Invalid Message Received Interrupt Enable bit bit 6 W
dsPIC33F REGISTER 20-8: R-0 CiEC: ECAN TRANSMIT/RECEIVE ERROR COUNT REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 TERRCNT<7:0> bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 RERRCNT<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 TERRCNT<7:0>: Transmit Error Count bits bit 7-0 RERRCNT<7:0>: Receive Error Count bits © 2007 Microchip Technology Inc.
dsPIC33F REGISTER 20-9: CiCFG1: ECAN BAUD RATE CONFIGURATION REGISTER 1 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SJW<1:0> R/W-0 R/W-0 R/W-0 BRP<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Unimplemented: Read as ‘0’ bit 7-6 SJW<1:0>: Synchronization Jump Width bits 11 = Length is 4 x TQ 10 = Length is 3 x
dsPIC33F REGISTER 20-10: CiCFG2: ECAN BAUD RATE CONFIGURATION REGISTER 2 U-0 R/W-x U-0 U-0 U-0 — WAKFIL — — — R/W-x R/W-x R/W-x SEG2PH<2:0> bit 15 bit 8 R/W-x R/W-x SEG2PHTS SAM R/W-x R/W-x R/W-x SEG1PH<2:0> R/W-x R/W-x R/W-x PRSEG<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14 WAKFIL: Select CAN bus Line Fi
dsPIC33F REGISTER 20-11: CiFEN1: ECAN ACCEPTANCE FILTER ENABLE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTEN15 FLTEN14 FLTEN13 FLTEN12 FLTEN11 FLTEN10 FLTEN9 FLTEN8 bit 15 bit 8 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 FLTEN7 FLTEN6 FLTEN5 FLTEN4 FLTEN3 FLTEN2 FLTEN1 FLTEN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unkno
dsPIC33F REGISTER 20-13: CiBUFPNT2: ECAN FILTER 4-7 BUFFER POINTER REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F7BP<3:0> R/W-0 R/W-0 R/W-0 F6BP<3:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F5BP<3:0> R/W-0 R/W-0 R/W-0 F4BP<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 F7BP<3:0>: RX Buffer Written when Filter 7 Hits bits bit 11-8 F6BP<3:0>: RX Buffer Written when Fil
dsPIC33F REGISTER 20-15: CiBUFPNT4: ECAN FILTER 12-15 BUFFER POINTER REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F15BP<3:0> R/W-0 R/W-0 R/W-0 F14BP<3:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F13BP<3:0> R/W-0 R/W-0 R/W-0 F12BP<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 F15BP<3:0>: RX Buffer Written when Filter 15 Hits bits bit 11-8 F14BP<3:0>: RX Buffer Written
dsPIC33F REGISTER 20-16: CiRXFnSID: ECAN ACCEPTANCE FILTER n STANDARD IDENTIFIER (n = 0, 1, ...
dsPIC33F REGISTER 20-18: CiFMSKSEL1: ECAN FILTER 7-0 MASK SELECTION REGISTER R/W-0 R/W-0 F7MSK<1:0> R/W-0 R/W-0 R/W-0 F6MSK<1:0> R/W-0 R/W-0 F5MSK<1:0> R/W-0 F4MSK<1:0> bit 15 bit 8 R/W-0 R/W-0 F3MSK<1:0> R/W-0 R/W-0 R/W-0 F2MSK<1:0> R/W-0 R/W-0 F1MSK<1:0> R/W-0 F0MSK<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 F7MSK<1:0>: Mask Source for Filter 7 bit bit 13
dsPIC33F REGISTER 20-19: CiRXMnSID: ECAN ACCEPTANCE FILTER MASK n STANDARD IDENTIFIER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 15 bit 8 R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x SID2 SID1 SID0 — MIDE — EID17 EID16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 SID<10:0>: Standard Identif
dsPIC33F REGISTER 20-21: CiRXFUL1: ECAN RECEIVE BUFFER FULL REGISTER 1 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10 RXFUL9 RXFUL8 bit 15 bit 8 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXFUL7 RXFUL6 RXFUL5 RXFUL4 RXFUL3 RXFUL2 RXFUL1 RXFUL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknow
dsPIC33F REGISTER 20-23: CiRXOVF1: ECAN RECEIVE BUFFER OVERFLOW REGISTER 1 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF9 RXOVF8 bit 15 bit 8 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXOVF7 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is un
dsPIC33F REGISTER 20-25: CiTRmnCON: ECAN TX/RX BUFFER m CONTROL REGISTER (m = 0,2,4,6; n = 1,3,5,7) R/W-0 R-0 R-0 R-0 R/W-0 R/W-0 TXENn TXABTn TXLARBn TXERRn TXREQn RTRENn R/W-0 R/W-0 TXnPRI<1:0> bit 15 bit 8 R/W-0 R-0 TXENm (1) TXABTm R-0 R-0 R/W-0 R/W-0 TXLARBm(1) TXERRm(1) TXREQm RTRENm R/W-0 R/W-0 TXmPRI<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit i
dsPIC33F Note: The buffers, SID, EID, DLC, Data Field and Receive Status registers are located in DMA RAM. REGISTER 20-26: CiTRBnSID: ECAN BUFFER n STANDARD IDENTIFIER (n = 0, 1, ...
dsPIC33F REGISTER 20-28: CiTRBnDLC: ECAN BUFFER n DATA LENGTH CONTROL (n = 0, 1, ...
dsPIC33F REGISTER 20-30: CiTRBnSTAT: ECAN RECEIVE BUFFER n STATUS (n = 0, 1, ...
dsPIC33F NOTES: DS70165E-page 260 Preliminary © 2007 Microchip Technology Inc.
dsPIC33F 21.0 Note: 21.1 DATA CONVERTER INTERFACE (DCI) MODULE 21.2.3 The Serial Data Input (CSDI) pin is configured as an input only pin when the module is enabled. This data sheet summarizes the features of this group of dsPIC33F devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC30F Family Reference Manual” (DS70046).
dsPIC33F FIGURE 21-1: DCI MODULE BLOCK DIAGRAM BCG Control bits SCKD FOSC/4 Sample Rate CSCK Generator FSD Word Size Selection bits Frame Length Selection bits 16-bit Data Bus DCI Mode Selection bits Frame Synchronization Generator COFS Receive Buffer Registers w/Shadow DCI Buffer Control Unit 15 Transmit Buffer Registers w/Shadow 0 DCI Shift Register CSDI CSDO DS70165E-page 262 Preliminary © 2007 Microchip Technology Inc.
dsPIC33F 21.3 21.3.1 21.3.4 DCI Module Operation MODULE ENABLE The DCI module is enabled or disabled by setting/ clearing the DCIEN control bit in the DCICON1 SFR. Clearing the DCIEN control bit has the effect of resetting the module. In particular, all counters associated with CSCK generation, frame sync and the DCI buffer control unit are reset. FRAME SYNC MODE CONTROL BITS The type of frame sync signal is selected using the Frame Synchronization mode control bits (COFSM<1:0>) in the DCICON1 SFR.
dsPIC33F 21.3.6 SLAVE FRAME SYNC OPERATION When the DCI module is operating as a frame sync slave (COFSD = 1), data transfers are controlled by the Codec device attached to the DCI module. The COFSM control bits control how the DCI module responds to incoming COFS signals. In the Multi-Channel mode, a new data frame transfer will begin one CSCK cycle after the COFS pin is sampled high (see Figure 21-2). The pulse on the COFS pin resets the frame sync generator logic.
dsPIC33F 21.3.7 BIT CLOCK GENERATOR EQUATION 21-2: The DCI module has a dedicated 12-bit time base that produces the bit clock. The bit clock rate (period) is set by writing a non-zero 12-bit value to the BCG<11:0> control bits in the DCICON3 SFR. When the BCG<11:0> bits are set to zero, the bit clock will be disabled. If the BCG<11:0> bits are set to a nonzero value, the bit clock generator is enabled.
dsPIC33F 21.3.8 SAMPLE CLOCK EDGE CONTROL BIT 21.3.11 The sample clock edge (CSCKE) control bit determines the sampling edge for the CSCK signal. If the CSCK bit is cleared (default), data will be sampled on the falling edge of the CSCK signal. The AC-Link protocols and most Multi-Channel formats require that data be sampled on the falling edge of the CSCK signal. If the CSCK bit is set, data will be sampled on the rising edge of CSCK.
dsPIC33F 21.3.14 BUFFER LENGTH CONTROL 21.3.16 The amount of data that is buffered between interrupts is determined by the Buffer Length (BLEN<1:0>) control bits in the DCICON2 SFR. The size of the transmit and receive buffers can vary from 1 to 4 data words using the BLEN control bits. The BLEN control bits are compared to the current value of the DCI buffer control unit address counter. When the 2 LSbs of the DCI address counter match the BLEN<1:0> value, the buffer control unit will be reset to ‘0’.
dsPIC33F 21.3.18 SLOT STATUS BITS 21.4 The SLOT<3:0> status bits in the DCISTAT SFR indicate the current active time slot. These bits will correspond to the value of the frame sync generator counter. The user may poll these status bits in software when a DCI interrupt occurs to determine what time slot data was last received and which time slot data should be loaded into the TXBUF registers. 21.3.19 CSDO MODE BIT The CSDOM control bit controls the behavior of the CSDO pin during unused transmit slots.
dsPIC33F 21.6.2 20-BIT AC-LINK MODE 21.7.1 The 20-bit AC-Link mode allows all bits in the data time slots to be transmitted and received but does not maintain data alignment in the TXBUF and RXBUF registers. The 20-bit AC-Link mode functions similar to the MultiChannel mode of the DCI module, except for the duty cycle of the frame synchronization signal. The AC-Link frame synchronization signal should remain high for 16 CSCK cycles and should be low for the following 240 cycles.
dsPIC33F REGISTER 21-1: DCICON1: DCI CONTROL REGISTER 1 R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 DCIEN — DCISIDL — DLOOP CSCKD CSCKE COFSD bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 UNFM CSDOM DJST — — — R/W-0 R/W-0 COFSM<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 DCIEN: DCI Module Enable bit 1 = Module is enabled 0 = Module is d
dsPIC33F REGISTER 21-2: DCICON2: DCI CONTROL REGISTER 2 U-0 U-0 U-0 U-0 — — — — R/W-0 R/W-0 U-0 R/W-0 — COFSG3 BLEN<1:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 — COFSG<2:0> R/W-0 R/W-0 R/W-0 WS<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 Reserved: Read as ‘0’ bit 11-10 BLEN<1:0>: Buffer Length Control bits 11 = Four data words will be buffered between
dsPIC33F REGISTER 21-3: DCICON3: DCI CONTROL REGISTER 3 U-0 U-0 U-0 U-0 — — — — R/W-0 R/W-0 R/W-0 R/W-0 BCG<11:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BCG<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 Reserved: Read as ‘0’ bit 11-0 BCG<11:0>: DCI bit Clock Generator Control bits DS70165E-page 272 Preliminary x = Bit is unknown © 200
dsPIC33F REGISTER 21-4: DCISTAT: DCI STATUS REGISTER U-0 U-0 U-0 U-0 — — — — R-0 R-0 R-0 R-0 SLOT<3:0> bit 15 bit 8 U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 — — — — ROV RFUL TUNF TMPTY bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 Reserved: Read as ‘0’ bit 11-8 SLOT<3:0>: DCI Slot Status bits 1111 = Slot #15 is currently active ••• 0010 = Slot #2 is currently active
dsPIC33F REGISTER 21-5: RSCON: DCI RECEIVE SLOT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RSE15 RSE14 RSE13 RSE12 RSE11 RSE10 RSE9 RSE8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RSE7 RSE6 RSE5 RSE4 RSE3 RSE2 RSE1 RSE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown RSE<15:0>: Receive Slot Enable bi
dsPIC33F 22.0 Note: 10-BIT/12-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) 22.2 The following configuration steps should be performed. 1. This data sheet summarizes the features of this group of dsPIC33F devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC30F Family Reference Manual” (DS70046). The dsPIC33F devices have up to 32 ADC input channels.
dsPIC33F FIGURE 22-1: ADC1 MODULE BLOCK DIAGRAM AVDD VREF+(1) AVSS VREF-(1) AN1 AN4 AN1 AN7 AN10 VREFAN2 AN5 AN2 AN8 AN11 VREF- + - ADC1 CH2(2) AN4 00100 AN5 00101 AN6 00110 AN7 00111 AN8 01000 AN9 01001 AN10 01010 AN11 01011 AN30 11110 AN31 11111 VREFAN1 Conversion Result Conversion Logic S/H 16-bit ADC Output Buffer + - CH3(2) S/H CH1,CH2, CH3,CH0 Sample 00000 00001 00010 00011 AN3 Note 1: 2: - CH1(2) S/H Input Switches + - Sample/Sequence Control Bus Interf
dsPIC33F FIGURE 22-2: ADC2 MODULE BLOCK DIAGRAM(1) AVDD VREF+(2) AVSS VREF-(2) AN1 AN4 AN1 AN7 AN10 VREFAN2 AN5 AN2 AN8 AN11 VREF- + - ADC2 CH2(3) AN4 00100 AN5 00101 AN6 00110 AN7 00111 AN8 01000 AN9 01001 AN10 01010 AN11 01011 AN14 11110 AN15 11111 VREFAN1 Conversion Result Conversion Logic S/H 16-bit ADC Output Buffer + - CH3(3) S/H CH1,CH2, CH3,CH0 Sample 00000 00001 00010 00011 AN3 Note 1: 2: 3: - CH1(3) S/H Input Switches + - Sample/Sequence Control Bus
dsPIC33F EQUATION 22-1: ADC CONVERSION CLOCK PERIOD TAD = TCY(ADCS + 1) ADCS = FIGURE 22-3: TAD –1 TCY ADC TRANSFER FUNCTION (10-BIT EXAMPLE) Output Code 11 1111 1111 (= 1023) 11 1111 1110 (= 1022) 10 0000 0011 (= 515) 10 0000 0010 (= 514) 10 0000 0001 (= 513) 10 0000 0000 (= 512) 01 1111 1111 (= 511) 01 1111 1110 (= 510) 01 1111 1101 (= 509) 00 0000 0001 (= 1) 00 0000 0000 (= 0) VREFL VREFL + VREFH – VREFL VREFL + 1024 512 * (VREFH – VREFL) 1024 VREFL + 1023 * (VREFH – VREFL) VREFH 1024 (VI
dsPIC33F REGISTER 22-1: ADxCON1: ADCx CONTROL REGISTER 1 (where x = 1 or 2) R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 ADON — ADSIDL ADDMABM — AD12B R/W-0 R/W-0 FORM<1:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 SSRC<2:0> U-0 R/W-0 R/W-0 R/W-0 HC,HS R/C-0 HC, HS — SIMSAM ASAM SAMP DONE bit 7 bit 0 Legend: HC = Cleared by hardware HS = Set by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is
dsPIC33F REGISTER 22-1: ADxCON1: ADCx CONTROL REGISTER 1 (CONTINUED)(where x = 1 or 2) bit 3 SIMSAM: Simultaneous Sample Select bit (only applicable when CHPS<1:0> = 01 or 1x) When AD12B = 1, SIMSAM is: U-0, Unimplemented, Read as ‘0’ 1 = Samples CH0, CH1, CH2, CH3 simultaneously (when CHPS<1:0> = 1x); or Samples CH0 and CH1 simultaneously (when CHPS<1:0> = 01) 0 = Samples multiple channels individually in sequence bit 2 ASAM: ADC Sample Auto-Start bit 1 = Sampling begins immediately after last convers
dsPIC33F REGISTER 22-2: R/W-0 ADxCON2: ADCx CONTROL REGISTER 2 (where x = 1 or 2) R/W-0 R/W-0 VCFG<2:0> U-0 U-0 R/W-0 — — CSCNA R/W-0 R/W-0 CHPS<1:0> bit 15 bit 8 R-0 U-0 BUFS — R/W-0 R/W-0 R/W-0 R/W-0 SMPI<3:0> R/W-0 R/W-0 BUFM ALTS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-13 x = Bit is unknown VCFG<2:0>: Converter Voltage Reference Configuration bits ADREF+
dsPIC33F REGISTER 22-2: bit 0 ADxCON2: ADCx CONTROL REGISTER 2 (CONTINUED) (where x = 1 or 2) ALTS: Alternate Input Sample Mode Select bit 1 = Uses channel input selects for Sample A on first sample and Sample B on next sample 0 = Always uses channel input selects for Sample A DS70165E-page 282 Preliminary © 2007 Microchip Technology Inc.
dsPIC33F REGISTER 22-3: ADxCON3: ADCx CONTROL REGISTER 3 R/W-0 U-0 U-0 ADRC — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SAMC<4:0> bit 15 bit 8 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADCS<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ADRC: ADC Conversion Clock Source bit 1 = ADC internal RC clock 0 = Clock derived from system clock bit 14-13 Unimplemented: Read a
dsPIC33F REGISTER 22-4: ADxCON4: ADCx CONTROL REGISTER 4 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0 R/W-0 R/W-0 DMABL<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 DMABL<2:0>: Selects Number of DMA Buffer Locations per Analog Input bits 111 = Al
dsPIC33F REGISTER 22-5: ADxCHS123: ADCx INPUT CHANNEL 1, 2, 3 SELECT REGISTER U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0 R/W-0 CH123NB<1:0> R/W-0 CH123SB bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0 R/W-0 CH123NA<1:0> R/W-0 CH123SA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-9 CH123NB<1:0>: Channel 1, 2, 3
dsPIC33F REGISTER 22-6: ADxCHS0: ADCx INPUT CHANNEL 0 SELECT REGISTER R/W-0 U-0 U-0 CH0NB — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0SB<4:0> bit 15 bit 8 R/W-0 U-0 U-0 CH0NA — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0SA<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 CH0NB: Channel 0 Negative Input Select for Sample B bit Same definition as bit 7.
dsPIC33F REGISTER 22-7: ADxCSSH: ADCx INPUT SCAN SELECT REGISTER HIGH(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSS31 CSS30 CSS29 CSS28 CSS27 CSS26 CSS25 CSS24 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSS23 CSS22 CSS21 CSS20 CSS19 CSS18 CSS17 CSS16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 Note 1: x = Bit is unknown CSS<31
dsPIC33F REGISTER 22-9: AD1PCFGH: ADC1 PORT CONFIGURATION REGISTER HIGH(1,2) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PCFG31 PCFG30 PCFG29 PCFG28 PCFG27 PCFG26 PCFG25 PCFG24 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PCFG23 PCFG22 PCFG21 PCFG20 PCFG19 PCFG18 PCFG17 PCFG16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 1
dsPIC33F 23.0 SPECIAL FEATURES Note: The device Configuration register map is shown in Table 23-1. This data sheet summarizes the features of this group of dsPIC33F devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC30F Family Reference Manual” (DS70046). The individual Configuration bit descriptions for the FBS, FSS, FGS, FOSCSEL, FOSC, FWDT, FPOR and FICD Configuration registers are shown in Table 23-2.
dsPIC33F TABLE 23-2: dsPIC33F CONFIGURATION BITS DESCRIPTION Bit Field Register Description BWRP FBS Boot Segment Program Flash Write Protection 1 = Boot segment may be written 0 = Boot segment is write-protected BSS<2:0> FBS Boot Segment Program Flash Code Protection Size X11 = No Boot program Flash segment Boot space is 1K IW less VS 110 = Standard security; boot program Flash segment starts at End of VS, ends at 0007FEh 010 = High security; boot program Flash segment starts at End of VS, ends a
dsPIC33F TABLE 23-2: dsPIC33F CONFIGURATION BITS DESCRIPTION (CONTINUED) Bit Field Register SSS<2:0> FSS Description Secure Segment Program Flash Code Protection Size (FOR 128K and 256K DEVICES) X11 = No Secure program Flash segment Secure space is 8K IW less BS 110 = Standard security; secure program Flash segment starts at End of BS, ends at 0x003FFE 010 = High security; secure program Flash segment starts at End of BS, ends at 0x003FFE Secure space is 16K IW less BS 101 = Standard security; secure
dsPIC33F TABLE 23-2: dsPIC33F CONFIGURATION BITS DESCRIPTION (CONTINUED) Bit Field Register GWRP FGS IESO FOSCSEL Two-speed Oscillator Start-up Enable bit 1 = Start-up device with FRC, then automatically switch to the user-selected oscillator source when ready 0 = Start-up device with user-selected oscillator source TEMP FOSCSEL Temperature Protection Enable bit 1 = Temperature protection disabled 0 = Temperature protection enabled FNOSC<2:0> FOSCSEL Initial Oscillator Source Selection bits 11
dsPIC33F TABLE 23-2: Bit Field Register Description PWMPIN FPOR Motor Control PWM Module Pin Mode bit 1 = PWM module pins controlled by PORT register at device Reset (tri-stated) 0 = PWM module pins controlled by PWM module at device Reset (configured as output pins) HPOL FPOR Motor Control PWM High Side Polarity bit 1 = PWM module high side output pins have active-high output polarity 0 = PWM module high side output pins have active-low output polarity LPOL FPOR Motor Control PWM Low Side Polari
dsPIC33F 23.3 Watchdog Timer (WDT) For dsPIC33F devices, the WDT is driven by the LPRC oscillator. When the WDT is enabled, the clock source is also enabled. The nominal WDT clock source from LPRC is 32 kHz. This feeds a prescaler than can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The prescaler is set by the WDTPRE Configuration bit. With a 32 kHz input, the prescaler yields a nominal WDT time-out period (TWDT) of 1 ms in 5-bit mode, or 4 ms in 7-bit mode.
dsPIC33F 23.4 JTAG Interface 23.7 In-Circuit Debugger dsPIC33F devices implement a JTAG interface, which supports boundary scan device testing, as well as in-circuit programming. Detailed information on the interface will be provided in future revisions of the document. When MPLAB® ICD 2 is selected as a debugger, the in-circuit debugging functionality is enabled. This function allows simple debugging functions when used with MPLAB IDE.
dsPIC33F NOTES: DS70165E-page 296 Preliminary © 2007 Microchip Technology Inc.
dsPIC33F 24.0 Note: INSTRUCTION SET SUMMARY This data sheet summarizes the features of this group of dsPIC33F devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC30F Family Reference Manual” (DS70046).
dsPIC33F All instructions are a single word, except for certain double-word instructions, which were made doubleword instructions so that all the required information is available in these 48 bits. In the second word, the 8 MSbs are ‘0’s. If this second word is executed as an instruction (by itself), it will execute as a NOP. Most single-word instructions are executed in a single instruction cycle, unless a conditional test is true, or the program counter is changed as a result of the instruction.
dsPIC33F TABLE 24-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED) Field Description Wm*Wm Multiplicand and Multiplier working register pair for Square instructions ∈ {W4 * W4,W5 * W5,W6 * W6,W7 * W7} Wm*Wn Multiplicand and Multiplier working register pair for DSP instructions ∈ {W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7} Wn One of 16 working registers ∈ {W0..W15} Wnd One of 16 destination working registers ∈ {W0..W15} Wns One of 16 source working registers ∈ {W0..
dsPIC33F TABLE 24-2: Base Instr # 1 2 3 4 5 6 7 8 9 INSTRUCTION SET OVERVIEW Assembly Mnemonic ADD ADDC AND ASR BCLR BRA BSET BSW BTG Assembly Syntax Description # of # of Words Cycles Status Flags Affected ADD Acc Add Accumulators 1 1 ADD f f = f + WREG 1 1 OA,OB,SA,SB C,DC,N,OV,Z ADD f,WREG WREG = f + WREG 1 1 C,DC,N,OV,Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C,DC,N,OV,Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C,DC,N,OV,Z ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C,DC,N
dsPIC33F TABLE 24-2: Base Instr # 10 11 12 13 Assembly Mnemonic BTSC BTSS BTST BTSTS 14 CALL 15 CLR 16 CLRWDT 17 COM 18 19 20 INSTRUCTION SET OVERVIEW (CONTINUED) CP CP0 CPB Assembly Syntax Description # of # of Words Cycles Status Flags Affected BTSC f,#bit4 Bit Test f, Skip if Clear 1 1 (2 or 3) None BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1 (2 or 3) None BTSS f,#bit4 Bit Test f, Skip if Set 1 1 (2 or 3) None BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 (2
dsPIC33F TABLE 24-2: Base Instr # 29 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic DIV Assembly Syntax # of # of Words Cycles Description Status Flags Affected DIV.S Wm,Wn Signed 16/16-bit Integer Divide 1 18 N,Z,C,OV DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N,Z,C,OV DIV.U Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N,Z,C,OV DIV.
dsPIC33F TABLE 24-2: Base Instr # 48 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic MPY Assembly Syntax Description # of # of Words Cycles Status Flags Affected MPY Wm*Wn,Acc,Wx,Wxd,Wy,Wyd Multiply Wm by Wn to Accumulator 1 1 OA,OB,OAB, SA,SB,SAB MPY Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square Wm to Accumulator 1 1 OA,OB,OAB, SA,SB,SAB 49 MPY.N MPY.
dsPIC33F TABLE 24-2: Base Instr # 66 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic RRNC Assembly Syntax f f = Rotate Right (No Carry) f 1 1 N,Z f,WREG WREG = Rotate Right (No Carry) f 1 1 N,Z RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N,Z SAC Acc,#Slit4,Wdo Store Accumulator 1 1 None SAC.
dsPIC33F 25.0 DEVELOPMENT SUPPORT 25.
dsPIC33F 25.2 MPASM Assembler 25.5 The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging.
dsPIC33F 25.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator 25.9 The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment.
dsPIC33F 25.11 PICSTART Plus Development Programmer 25.13 Demonstration, Development and Evaluation Boards The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins.
dsPIC33F 26.0 ELECTRICAL CHARACTERISTICS This section provides an overview of dsPIC33F electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the dsPIC33F family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability.
dsPIC33F 26.1 DC Characteristics TABLE 26-1: OPERATING MIPS VS. VOLTAGE Characteristic DC5 TABLE 26-2: VDD Range (in Volts) Temp Range (in °C) Max MIPS 3.0-3.
dsPIC33F TABLE 26-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial DC CHARACTERISTICS Parameter No.
dsPIC33F TABLE 26-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial DC CHARACTERISTICS Parameter No.
dsPIC33F TABLE 26-8: DC CHARACTERISTICS: DOZE CURRENT (IDOZE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial DC CHARACTERISTICS Doze Ratio Parameter No. Typical(1) Max DC70a 42 — 1:2 DC70f 26 — 1:64 DC70g 25 — 1:128 DC71a 41 — 1:2 DC71f 25 — 1:64 DC71g 24 — 1:128 Note 1: Units Conditions mA 25°C 3.3V 40 MIPS mA 85°C Data in the Typical column is at 3.3V, 25°C unless otherwise stated.
dsPIC33F TABLE 26-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial DC CHARACTERISTICS Param Symbol No. VIL Characteristic Min Typ(1) Max Units Conditions Input Low Voltage DI10 I/O pins VSS — 0.2 VDD V DI15 MCLR VSS — 0.2 VDD V DI16 OSC1 (XT mode) VSS — 0.2 VDD V DI17 OSC1 (HS mode) VSS — 0.2 VDD V DI18 SDAx, SCLx VSS — 0.
dsPIC33F TABLE 26-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial DC CHARACTERISTICS Param Symbol No. VOL Characteristic Typ(1) Min Max Units Conditions Output Low Voltage DO10 I/O ports — — 0.4 V IOL = TBD, VDD = 3.3V DO16 OSC2/CLKO — — 0.4 V IOL = TBD, VDD = 3.3V I/O ports 2.4 — — V IOH = -3.0 mA, VDD = 3.3V OSC2/CLKO 2.4 — — V IOH = -1.
dsPIC33F 26.2 AC Characteristics and Timing Parameters The information contained in this section defines dsPIC33F AC characteristics and timing parameters. TABLE 26-13: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Operating voltage VDD range as described in Section 26.0 “Electrical Characteristics”.
dsPIC33F FIGURE 26-2: EXTERNAL CLOCK TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 OS20 OS30 OS25 OS31 OS30 OS31 CLKO OS41 OS40 TABLE 26-15: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial AC CHARACTERISTICS Param No. OS10 OS20 Symb FIN TOSC Min Typ(1) Max Units External CLKI Frequency (External clocks allowed only in EC and ECPLL modes) 0.
dsPIC33F TABLE 26-16: PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 3.6V) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial AC CHARACTERISTICS Param No. Characteristic(1) Symbol Min Typ(2) Max Units OS50 FPLLI PLL Voltage Controlled Oscillator (VCO) Input Frequency Range(2) 0.
dsPIC33F FIGURE 26-3: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) New Value Old Value DO31 DO32 Note: Refer to Figure 26-1 for load conditions. TABLE 26-19: CLKO AND I/O TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial AC CHARACTERISTICS Param No.
dsPIC33F FIGURE 26-4: VDD RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING CHARACTERISTICS SY12 MCLR SY10 Internal POR SY11 PWRT Time-out OSC Time-out SY30 Internal Reset Watchdog Timer Reset SY13 SY20 SY13 I/O Pins SY35 FSCM Delay Note: Refer to Figure 26-1 for load conditions. DS70165E-page 320 Preliminary © 2007 Microchip Technology Inc.
dsPIC33F TABLE 26-20: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C AC CHARACTERISTICS Param Symbol No. Characteristic(1) Min Typ(2) Max Units 2 — — μs -40°C to +85°C 0.75 1.5 3 6 12 24 48 96 1 2 4 8 16 32 64 128 1.25 2.
dsPIC33F FIGURE 26-5: TIMER1, 2, 3, 4, 5, 6, 7, 8 AND 9 EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx11 Tx10 Tx15 OS60 Tx20 TMRx Note: Refer to Figure 26-1 for load conditions. TABLE 26-21: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C AC CHARACTERISTICS Param No.
dsPIC33F TABLE 26-22: TIMER2, TIMER4, TIMER6 AND TIMER8 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C AC CHARACTERISTICS Param No. TB10 TB11 TB15 Symbol TtxH TtxL TtxP Characteristic TxCK High Time TxCK Low Time Min Typ Max Units Synchronous, no prescaler 0.5 TCY + 20 — — ns Synchronous, with prescaler 10 — — ns Synchronous, no prescaler 0.
dsPIC33F FIGURE 26-6: TIMERQ (QEI MODULE) EXTERNAL CLOCK TIMING CHARACTERISTICS QEB TQ11 TQ10 TQ15 TQ20 POSCNT TABLE 26-24: QEI MODULE EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C AC CHARACTERISTICS Param No.
dsPIC33F FIGURE 26-7: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS ICx IC10 IC11 IC15 Note: Refer to Figure 26-1 for load conditions. TABLE 26-25: INPUT CAPTURE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C AC CHARACTERISTICS Param No. Characteristic(1) Symbol IC10 TccL ICx Input Low Time IC11 TccH ICx Input High Time IC15 TccP ICx Input Period No Prescaler Min Max Units 0.
dsPIC33F FIGURE 26-9: OC/PWM MODULE TIMING CHARACTERISTICS OC20 OCFA/OCFB OC15 OCx TABLE 26-27: SIMPLE OC/PWM MODE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C AC CHARACTERISTICS Param No.
dsPIC33F FIGURE 26-10: MOTOR CONTROL PWM MODULE FAULT TIMING CHARACTERISTICS MP30 FLTA/B MP20 PWMx FIGURE 26-11: MOTOR CONTROL PWM MODULE TIMING CHARACTERISTICS MP11 MP10 PWMx Note: Refer to Figure 26-1 for load conditions. TABLE 26-28: MOTOR CONTROL PWM MODULE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C AC CHARACTERISTICS Param No.
dsPIC33F FIGURE 26-12: QEA/QEB INPUT CHARACTERISTICS TQ36 QEA (input) TQ30 TQ31 TQ35 QEB (input) TQ41 TQ40 TQ30 TQ31 TQ35 QEB Internal TABLE 26-29: QUADRATURE DECODER TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C AC CHARACTERISTICS Param No.
dsPIC33F FIGURE 26-13: QEI MODULE INDEX PULSE TIMING CHARACTERISTICS QEA (input) QEB (input) Ungated Index TQ50 TQ51 Index Internal TQ55 Position Counter Reset TABLE 26-30: QEI INDEX PULSE TIMING REQUIREMENTS AC CHARACTERISTICS Param No. Standard Operating Conditions: 3.0V to 3.
dsPIC33F FIGURE 26-14: SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS SCKx (CKP = 0) SP11 SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 Bit 14 - - - - - -1 MSb SDOx SP31 SDIx LSb SP30 MSb In LSb In Bit 14 - - - -1 SP40 SP41 Note: Refer to Figure 26-1 for load conditions. TABLE 26-31: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C AC CHARACTERISTICS Param No.
dsPIC33F FIGURE 26-15: SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS SP36 SCKX (CKP = 0) SP11 SP10 SP21 SP20 SP20 SP21 SCKX (CKP = 1) SP35 SP40 SDIX LSb Bit 14 - - - - - -1 MSb SDOX SP30,SP31 MSb In Bit 14 - - - -1 LSb In SP41 Note: Refer to Figure 26-1 for load conditions. TABLE 26-32: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C AC CHARACTERISTICS Param No.
dsPIC33F FIGURE 26-16: SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS SSX SP52 SP50 SCKX (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCKX (CKP = 1) SP35 MSb SDOX LSb Bit 14 - - - - - -1 SP51 SP30,SP31 SDIX Bit 14 - - - -1 MSb In LSb In SP41 SP40 Note: Refer to Figure 26-1 for load conditions. TABLE 26-33: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.
dsPIC33F TABLE 26-33: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS (CONTINUED) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C AC CHARACTERISTICS Param No. SP52 Characteristic(1) Symbol TscH2ssH SSx after SCKx Edge TscL2ssH Note 1: 2: 3: Min Typ(2) Max Units Conditions 1.5 TCY +40 — — ns — These parameters are characterized but not tested in manufacturing. Data in “Typ” column is at 5V, 25°C unless otherwise stated.
dsPIC33F TABLE 26-34: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C AC CHARACTERISTICS Param No.
dsPIC33F FIGURE 26-18: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCLx IM31 IM34 IM30 IM33 SDAx Stop Condition Start Condition Note: Refer to Figure 26-1 for load conditions. FIGURE 26-19: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM21 IM11 IM10 SCLx IM11 IM26 IM10 IM25 IM33 SDAx In IM40 IM40 IM45 SDAx Out Note: Refer to Figure 26-1 for load conditions. © 2007 Microchip Technology Inc.
dsPIC33F TABLE 26-35: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C AC CHARACTERISTICS Param Symbol No.
dsPIC33F FIGURE 26-20: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCLx IS34 IS31 IS30 IS33 SDAx Stop Condition Start Condition FIGURE 26-21: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS21 IS11 IS10 SCLx IS30 IS26 IS31 IS25 IS33 SDAx In IS40 IS40 IS45 SDAx Out © 2007 Microchip Technology Inc.
dsPIC33F TABLE 26-36: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C AC CHARACTERISTICS Param No.
dsPIC33F FIGURE 26-22: DCI MODULE (MULTI-CHANNEL, I2S MODES) TIMING CHARACTERISTICS CSCK (SCKE = 0) CS11 CS10 CS21 CS20 CS20 CS21 CSCK (SCKE = 1) COFS CS55 CS56 CS35 CS51 CSDO 70 CS50 High-Z LSb MSb CS30 CSDI High-Z CS31 LSb In MSb In CS40 CS41 Note: Refer to Figure 26-1 for load conditions. © 2007 Microchip Technology Inc.
dsPIC33F TABLE 26-37: DCI MODULE (MULTI-CHANNEL, I2S MODES) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C AC CHARACTERISTICS Param No.
dsPIC33F FIGURE 26-23: DCI MODULE (AC-LINK MODE) TIMING CHARACTERISTICS BIT_CLK (CSCK) CS61 CS60 CS62 CS21 CS20 CS71 CS70 CS72 SYNC (COFS) CS76 CS75 CS80 SDOx (CSDO) LSb MSb LSb CS76 SDIx (CSDI) CS75 MSb In CS65 CS66 © 2007 Microchip Technology Inc.
dsPIC33F TABLE 26-38: DCI MODULE (AC-LINK MODE) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C AC CHARACTERISTICS Param No. Symbol Characteristic(1,2) Min Typ(3) Max Units Conditions — CS60 TBCLKL BIT_CLK Low Time 36 40.7 45 ns CS61 TBCLKH BIT_CLK High Time 36 40.7 45 ns CS62 TBCLK BIT_CLK Period — 81.
dsPIC33F FIGURE 26-24: CiTx Pin (output) CAN MODULE I/O TIMING CHARACTERISTICS New Value Old Value CA10 CA11 CiRx Pin (input) CA20 TABLE 26-39: CAN MODULE I/O TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C AC CHARACTERISTICS Param No.
dsPIC33F TABLE 26-40: ADC MODULE SPECIFICATIONS (CONTINUED) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C AC CHARACTERISTICS Param No. Symbol Characteristic AD06 VREFL Reference Voltage Low AD07 VREF Absolute Reference Voltage AD08 IREF Current Drain Min. Typ Max. Units Conditions AVSS — AVDD – 1.7 V — AVSS – 0.3 — AVDD + 0.3 V — — 150 .001 200 1 μA μA ADC operating ADC off VREFL VREFH V See Note AVSS – 0.
dsPIC33F TABLE 26-40: ADC MODULE SPECIFICATIONS (CONTINUED) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ Max.
dsPIC33F FIGURE 26-25: ADC CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000) AD50 ADCLK Instruction Execution Set SAMP Clear SAMP SAMP ch0_dischrg ch0_samp ch1_dischrg ch1_samp eoc AD61 AD60 AD55 TSAMP AD55 CONV ADxIF Buffer(0) Buffer(1) 1 2 3 4 5 6 7 8 5 6 7 8 1 – Software sets ADxCON. SAMP to start sampling. 2 – Sampling starts after discharge period. TSAMP is described in Section 17 in the “dsPIC30F Family Reference Manual”.
dsPIC33F FIGURE 26-26: ADC CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001) AD50 ADCLK Instruction Execution Set ADON SAMP ch0_dischrg ch0_samp ch1_dischrg ch1_samp eoc TSAMP TSAMP AD55 TCONV AD55 CONV ADxIF Buffer(0) Buffer(1) 1 2 3 4 5 6 7 3 4 5 6 8 3 4 1 – Software sets ADxCON. ADON to start AD operation. 5 – Convert bit 0. 2 – Sampling starts after discharge period.
dsPIC33F TABLE 26-41: ADC CONVERSION (10-BIT MODE) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C AC CHARACTERISTICS Param Symbol No. Characteristic Min. Typ(1) Max.
dsPIC33F FIGURE 26-27: ADC CONVERSION (12-BIT MODE) TIMING CHARACTERISTICS (ASAM = 0, SSRC<2:0> = 000) AD50 ADCLK Instruction Execution Set SAMP Clear SAMP SAMP ch0_dischrg ch0_samp eoc AD61 AD60 TSAMP AD55 CONV ADxIF Buffer(0) 1 2 3 4 5 6 7 8 9 1 – Software sets ADxCON. SAMP to start sampling. 2 – Sampling starts after discharge period. TSAMP is described in the “dsPIC30F Family Reference Manual”, Section 17. 3 – Software clears ADxCON. SAMP to start conversion.
dsPIC33F TABLE 26-42: ADC CONVERSION (12-BIT MODE) TIMING REQUIREMENTS) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ Max.
dsPIC33F 27.0 PACKAGING INFORMATION 27.1 Package Marking Information 64-Lead TQFP (10x10x1 mm) Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN dsPIC33FJ 256GP706 -I/PT e3 0710017 80-Lead TQFP (12x12x1 mm) Example XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN dsPIC33FJ128 GP708-I/PT e3 0710017 100-Lead TQFP (12x12x1 mm) Example XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN dsPIC33FJ256 GP710-I/PT e3 0710017 100-Lead TQFP (14x14x1mm) Example XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Legend: XX...
dsPIC33F 27.2 Package Details The following sections give the technical details of the packages. 64-Lead Plastic Thin Quad Flatpack (PT) – 10x10x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 E e E1 N b NOTE 1 123 NOTE 2 α A c φ A2 β A1 L L1 Units Dimension Limits Number of Leads MILLIMETERS MIN N NOM MAX 64 Lead Pitch e Overall Height A – 0.
dsPIC33F 80-Lead Plastic Thin Quad Flatpack (PT) – 12x12x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 E e E1 N b NOTE 1 12 3 NOTE 2 c β φ L α A A2 A1 L1 Units Dimension Limits Number of Leads MILLIMETERS MIN N NOM MAX 80 Lead Pitch e Overall Height A – 0.50 BSC – Molded Package Thickness A2 0.95 1.00 1.05 Standoff A1 0.05 – 0.
dsPIC33F 100-Lead Plastic Thin Quad Flatpack (PT) – 12x12x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 e E E1 N b NOTE 1 1 23 NOTE 2 c α A φ L β A1 Units Dimension Limits Number of Leads A2 L1 MILLIMETERS MIN N NOM MAX 100 Lead Pitch e Overall Height A – 0.40 BSC – Molded Package Thickness A2 0.95 1.00 1.05 Standoff A1 0.05 – 0.
dsPIC33F 100-Lead Plastic Thin Quad Flatpack (PF) – 14x14x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 e E1 E b N NOTE 1 α 1 23 φ c β A NOTE 2 A2 A1 L L1 Units Dimension Limits Number of Leads MILLIMETERS MIN N NOM MAX 100 Lead Pitch e Overall Height A – 0.50 BSC – Molded Package Thickness A2 0.95 1.00 1.05 Standoff A1 0.05 – 0.
dsPIC33F NOTES: DS70165E-page 356 Preliminary © 2007 Microchip Technology Inc.
dsPIC33F APPENDIX A: REVISION HISTORY • Initial release of this document • Corrected mislabeled I2COV bit in I2CxCON register (see Register 18-1) • Removed AD26a, AD27a, AD28a, AD26b, AD27b, AD28b from Table 26-40 (ADC Module). Revision B (February 2006) Revision E (January 2007) • • • • • This revision includes updates to the packaging diagrams.
dsPIC33F NOTES: DS70165E-page 358 Preliminary © 2007 Microchip Technology Inc.
dsPIC33F INDEX A A/D Converter ................................................................... 275 DMA .......................................................................... 275 Initialization ............................................................... 275 Key Features............................................................. 275 AC Characteristics ............................................................ 316 Internal RC Accuracy ................................................
dsPIC33F Receive Status Bits ................................................... 267 Sample Clock Edge Control Bit................................. 266 Slave Frame Sync Operation .................................... 264 Slot Enable Bits Operation with Frame Sync ............ 266 Slot Status Bits.......................................................... 268 Synchronous Data Transfers .................................... 266 Transmit Slot Enable Bits..........................................
dsPIC33F Instruction-Based Power-Saving Modes ........................... 157 Idle ............................................................................ 158 Sleep......................................................................... 157 Internal RC Oscillator Use with WDT ........................................................... 294 Internet Address................................................................ 365 Interrupt Control and Status Registers................................ 91 IECx .
dsPIC33F Priority ....................................................................... 182 PWM Output and Polarity Control ..................................... 182 Output Pin Control .................................................... 182 PWM Special Event Trigger .............................................. 183 Postscaler ................................................................. 183 PWM Time Base ...............................................................
dsPIC33F IPC7 (Interrupt Priority Control 7) ............................. 121 IPC8 (Interrupt Priority Control 8) ............................. 122 IPC9 (Interrupt Priority Control 9) ............................. 123 NVMCOM (Flash Memory Control)............................. 79 OCxCON (Output Compare x Control) ..................... 174 OSCCON (Oscillator Control) ................................... 152 OSCTUN (FRC Oscillator Tuning) ............................ 155 OVDCON (Override Control) .............
dsPIC33F Timer2, Timer4, Timer6 and Timer8 External Clock Requirements.......................................... 323 Timer3, Timer5, Timer7 and Timer9 External Clock Requirements.......................................... 323 U UART Baud Rate Generator (BRG)............................................... 224 Break and Sync Transmit Sequence ........................ 225 Flow Control Using UxCTS and UxRTS Pins............ 225 Receiving in 8-bit or 9-bit Data Mode........................
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dsPIC33F READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
dsPIC33F PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. dsPIC 33 FJ 256 GP7 10 T I / PT - XXX Examples: a) Microchip Trademark Architecture Flash Memory Family b) Program Memory Size (KB) Product Group dsPIC33FJ256GP710I/PT: General-purpose dsPIC33, 64 KB program memory, 100-pin, Industrial temp., TQFP package. dsPIC33FJ64MC706I/PT-ES: Motor-control dsPIC33, 64 KB program memory, 64-pin, Industrial temp.
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