Datasheet

AN1208
DS01208A-page 4 © 2008 Microchip Technology Inc.
Digital Power Factor Correction
The inductor current (I
AC
), input rectified AC voltage
(V
AC
), and DC Output Voltage (V
DC
) are used as
feedback signals to implement the digital PFC. These
signals are scaled by hardware gains and are input to
the analog channels of the ADC module.
The PFC algorithm uses three control loops: the
voltage control loop, current control loop, and the
voltage feed forward control loop.
The voltage compensator uses the reference voltage
and actual output voltage as inputs to compute the
error and compensate for the variations in output
voltage. The output voltage is controlled by varying the
average value of the current amplitude signal.
The current amplitude signal is calculated digitally by
computing the product of the rectified input voltage, the
voltage error compensator output, and the voltage
feed-forward compensator output.
The rectified input voltage is multiplied to enable the
current signal to have the same shape as the input
voltage waveshape. The current signal should match
the rectified voltage as closely as possible to have a
high power factor.
The voltage feed-forward compensator is essential for
maintaining a constant output power for a given load
because it compensates for variations in the input
voltage. Once the current signal is computed, it is fed
to the current compensator. The output of the current
compensator determines the duty cycle of the PWM
pulses. The boost converter can be driven either by the
Output Compare module or the PWM module.
Refer to application note AN1106, Power Factor Cor-
rection in Power Conversion Applications Using the
dsPIC
®
DSC (DS01106), for information about the sys-
tem design and digital implementations of this control
method.
Sensorless Field Oriented Control
The phase currents, I
a
and I
b
, are used as feedback
signals to implement the Sensorless FOC technique.
The third phase current, I
c
, is calculated digitally. The
three-phase currents are first converted to a two-phase
stator system by using Clarke transformation before
being converted to a two-phase rotor system by using
Park transformation. This conversion provides two
computed current components: I
d
and I
q
. The
magnetizing flux is a function of the current I
d
and the
rotor torque is a function of
the current I
q
.
A position estimator estimates the rotor position and
speed information. The motor model uses voltages and
currents to estimate the position. The motor model
essentially has a position observer to indirectly derive
the rotor position. The PMSM model is based on a DC
motor model.
After the speed is determined by mathematical
estimation, the error between the desired speed and
the estimated speed is fed to the speed compensator.
The speed compensator produces an output that acts
as a reference to the I
q
compensator. For a permanent
magnet motor, the reference to the I
d
compensator is
zero value. The PI controllers for I
q and I
d
compensate
errors in the torque and flux, thereby producing V
d
and
V
q
as the output signals respectively.
The Inverse Park transformation and Space Vector
Modulation (SVM) techniques are applied to generate
the duty cycle for the Insulated Gate Bipolar Transistors
(IGBTs).The motor control PWM module is used to
generate PWM pulses.
Refer to application note AN1078, Sensorless Field
Oriented Control of PMSM Motors (DS01078), for
information about how to design, implement, and tune
the compensator.
The implementation details and the hardware
configuration details required to develop the integrated
system are discussed in the following sections.
INTEGRATED PFC AND SENSORLESS
FOC IMPLEMENTATION ON A dsPIC
DSC DEVICE
The following control parameters and routine are used,
when the integrated system is implemented by using a
dsPIC30F or dsPIC33F device:
• PFC PWM frequency: 80 kHz
• FOC PWM frequency: 8 kHz
• PFC Control loop frequency: 40 kHz
• FOC Control loop: 8 kHz
• Point of execution for PFC routine: ADC ISR
• Point of execution for FOC routines: PWM ISR
• Trigger Source to the ADC: Timer
Figure 3 shows the timing diagram of the integrated
PFC and Sensorless FOC system. Figure 4 through
Figure 6 shows the state flow diagram of the integrated
system.