Datasheet

dsPIC30F
DS70043F-page 6 © 2005 Microchip Technology Inc.
3.0 DEVICE OVERVIEW FOR
GENERAL PURPOSE AND
SENSOR FAMILIES
Figure 3-1 shows a sample device block diagram
typical of the dsPIC30F General Purpose Product
Family. Pin functionality and pinouts for this family are
shown in Appendix A.
FIGURE 3-1: dsPIC30F5013/6013A/6014A BLOCK DIAGRAM
Note: The device depicted in Figure 3-1 is repre-
sentative of this family. Other devices of
the same family may vary in terms of
number of pins and multiplexing of pin
functions. Typically, smaller devices in the
family contain a subset of the peripherals
present in the device(s) shown here.
Power-up
Timer
Oscillator
Start-up Timer
POR/BOR
Reset
Watchdog
Timer
Instruction
Decode &
Control
O
S
C
1
/
C
L
K
I
MCLR
VDD, VSS
Low Voltage
Detect
UART1,
CAN2
Timing
Generation
CAN1,
16
PCH PCL
16
Program Counter
ALU<16>
16
23
24
24
24
X Data Bus
IR
I
2
C™
DCI
PCU
12-bit ADC
Timers
Input
Capture
Module
Output
Compare
Module
16
16 16
16 x 16
W Reg Array
Divide
Unit
Engine
DSP
Decode
ROM Latch
16
Y Data Bus
Effective Address
X RAGU
X WAGU
Y AGU
AVDD, AVSS
UART2
SPI2
16
16
16
16
16
16
16
16
16
8
Interrupt
Controller
PSV & Table
Data Access
Control Block
Stack
Control
Logic
Loop
Control
Logic
Data LatchData Latch
Y Data
(4 Kbytes)
RAM
X Data
(4 Kbytes)
RAM
Address
Latch
Address
Latch
Control Signals
to Various Blocks
16
SPI1,
Address Latch
Program Memory
(144 Kbytes)
Data Latch
Data EEPROM
(4 Kbytes)
General Purpose Family Peripherals
I/O Ports
ABCDFG
System Integration
Central Processing Unit