Datasheet

dsPIC30F
DS70043F-page 30 © 2005 Microchip Technology Inc.
9.5 Input Capture Module
The Input Capture module is useful in applications
requiring Frequency (Period) and Pulse measurement.
The dsPIC30F devices support up to eight input
capture channels.
The Input Capture module captures the 16-bit value of
the selected time base register when an event occurs
at the ICx pin. The events that cause a capture event
are listed below in three categories:
1. Simple Capture Event modes:
- Capture timer value on every falling edge of
input at ICx pin
- Capture timer value on every rising edge of
input at ICx pin
2. Capture timer value on every edge (rising and
falling)
3. Prescaler Capture Event modes:
- Capture timer value on every 4th rising
edge of input at ICx pin
- Capture timer value on every 16th rising
edge of input at ICx pin
Each input capture channel can select between one of
two 16-bit timers (Timer2 or Timer3) for the time base.
The selected timer can use either an internal or an
external clock.
Other operational features include:
• Device wake-up from capture pin during CPU
Sleep and Idle modes
• Interrupt on input capture event
• 4-word FIFO buffer for capture values:
- Interrupt optionally generated after 1, 2, 3 or
4 buffer locations are filled
Input capture can also be used to provide additional
sources of external interrupts.
9.6 Output Compare/PWM Module
The Output Compare module features are quite useful
in applications that require controlled timing pulses or
PWM modulated pulse streams.
The Output Compare module has the ability to
compare the value of a selected time base with the
value of one or two compare registers (depending on
the Operation mode selected). Furthermore, it has the
ability to generate a single output pulse, or a repetitive
sequence of output pulses, on a compare match event.
Like most dsPIC30F peripherals, it also has the ability
to generate interrupts-on-compare match events.
The dsPIC30F device may have up to eight output
compare channels, designated OC1 through OC8.
Refer to the specific device data sheet for the number
of channels available in a particular device. All output
compare channels are functionally identical.
Each output compare channel can use one of two
selectable time bases. The time base is selected using
the OCTSEL bit (OCxCON<3>). An ‘x’ in the pin,
register or bit name denotes the specific output
compare channel. Refer to the device data sheet for the
specific timers that can be used with each output
compare channel number.
Each Output Compare module has the following modes
of operation:
• Single Compare Match mode
• Dual Compare Match mode generating:
- Single Output Pulse
- Continuous Output Pulses
• Simple Pulse Width Modulation mode:
- With Fault Protection Input
- Without Fault Protection Input
9.7 Data Converter Interface Module
The dsPIC30F Data Converter Interface (DCI) module
allows simple interfacing to devices such as audio
coder/decoders (codecs), A/D converters and D/A
converters.
The following interfaces are supported:
• Framed Synchronous Serial Transfer (Single or
Multi-Channel)
• Inter-IC Sound (I
2
S) Interface
• AC-Link (AC’97) Compliant mode
Many codecs intended for use in audio applications
support sampling rates between 8 kHz and 48 kHz and
use one of the interface protocols listed above. The
DCI automatically handles the interface timing
associated with these codecs. No overhead from the
CPU is required until the requested amount of data has
been transmitted and/or received by the DCI. Up to four
data words can be transferred between CPU interrupts.
The data word length for the DCI is programmable up
to 16 bits to match the data size of the dsPIC30F CPU.
However, many codecs have data word sizes greater
than 16 bits. Long data word lengths can be supported
by the DCI. The DCI is configured to transmit/receive
the long word in multiple 16-bit time slots. This
operation is transparent to the user, and the long data
word is stored in consecutive register locations.
Figure 9-4 is a block diagram of the DCI Module. The
DCI can support up to 16 time slots in a data frame, for
a maximum frame size of 256 bits. There are control
bits for each time slot in the data frame that determine
whether the DCI will transmit/receive during the time
slot.