Datasheet

© 2005 Microchip Technology Inc. DS70043F-page 29
dsPIC30F
FIGURE 9-3: QUADRATURE ENCODER INTERFACE BLOCK DIAGRAM
16-bit Up/Down Counter
Comparator/
Max Count Register
Quadrature
Programmable
Digital Filter
QEA
Programmable
Digital Filter
INDX
0
1
Up/Down
Existing Pin Logic
UPDN
3
Encoder
Programmable
Digital Filter
QEB
Interface Logic
QEIM<2:0>
Mode Select
3
(POSCNT)
(MAXCNT)
PCDOUT
QEIIF
Event
Flag
Reset
Equal
2
T
CY
1
0
TQCS
TQCKPS<1:0>
2
1, 8, 64, 256
Prescaler
Q
QD
CK
TQGATE
QEIM<2:0>
Synchronize
Det
1
0
Sleep Input
0
1
UPDN_SRC
QEICON<11>
Zero Detect