Datasheet

© 2005 Microchip Technology Inc. DS70043F-page 23
dsPIC30F
8.3 Power-Saving Modes
The dsPIC30F devices have two reduced power
modes that can be entered through execution of the
PWRSAV instruction.
• Sleep mode: The CPU, system clock source and
any peripherals that operate on the system clock
source are disabled. This is the lowest power
mode of the device.
• Idle mode: The CPU is disabled, but the system
clock source continues to operate. Peripherals
continue to operate, but can optionally be
disabled.
These modes provide an effective way to reduce power
consumption during periods when the CPU is not is
use.
8.3.1 SLEEP MODE
When the device enters Sleep mode:
• System clock source is shut down. If an on-chip
oscillator is used, it is turned off.
• Device current consumption is at minimum,
provided that no I/O pin is sourcing current.
• Fail-Safe Clock Monitor (FSCM) does not operate
during Sleep mode because the system clock
source is disabled.
• LPRC clock continues to run in Sleep mode if the
WDT is enabled.
• Low Voltage Detect circuit, if enabled, remains
operative during Sleep mode.
• BOR circuit, if enabled, remains operative during
Sleep mode.
• WDT, if enabled, is automatically cleared prior to
entering Sleep mode.
• Some peripherals may continue to operate in
Sleep mode. These peripherals include I/O pins
that detect a change in the input signal, or
peripherals that use an external clock input. Any
peripheral that is operating on the system clock
source is disabled in Sleep mode.
The processor exits (wakes up) from Sleep on one of
these events:
• Any interrupt source that is individually enabled.
• Any form of device Reset.
• A WDT time-out.
8.3.2 IDLE MODE
When the device enters Idle mode:
• CPU stops executing instructions.
• WDT is automatically cleared.
• System clock source remains active.
• Peripheral modules, by default, continue to
operate normally from the system clock source.
• Peripherals, optionally, can be shut down in Idle
mode using their ‘stop-in-idle’ control bit.
• If the WDT or FSCM is enabled, the LPRC also
remains active.
The processor wakes from Idle mode on these events:
• Any interrupt that is individually enabled.
• Any source of device Reset.
•A WDT Time-out.
Upon wake up from Idle, the clock is re-applied to the
CPU and instruction execution begins immediately
starting with the instruction following the PWRSAV
instruction, or the first instruction in the Interrupt
Service Routine (ISR).