Datasheet

dsPIC30F

6.3 Traps

Traps can be considered as non-maskable, nestable

interrupts that adhere to a fixed priority structure.

Traps are intended to provide the user a means to

correct erroneous operation during debug and when

operating within the application. If the user does not

intend to take corrective action in the event of a trap

error condition, these vectors must be loaded with the

address of a software routine that will reset the device.

Otherwise, the trap vector is programmed with the

address of a service routine that will correct the trap

condition.

The dsPIC30F has four implemented sources of

non-maskable traps:

• Oscillator Failure Trap

• Address Error Trap

• Stack Error Trap

• Arithmetic Error Trap

Many of these trap conditions can only be detected

when they happen. Consequently, the instruction that

caused the trap is allowed to complete before

exception processing begins. Therefore, the user may

have to correct the action of the instruction that

caused the trap.

Each trap source has a fixed priority as defined by its

position in the IVT. An oscillator failure trap has the

highest priority, while an arithmetic error trap has the

lowest priority.

Table 6-2 contains information about the trap vector.

6.4 Generating a Software Interrupt

Any available interrupt can be manually generated by

user software (even if the corresponding peripheral is

disabled), simply by enabling the interrupt and then

setting the interrupt flag bit when required.

TABLE 6-2: TRAP VECTORS

Vector Number IVT Address AIVT Address Trap Source

0 0x000004 0x000084 Reserved

1 0x000006 0x000086 Oscillator Failure

2 0x000008 0x000088 Address Error

3 0x00000A 0x00008A Stack Error

4 0x00000C 0x00008C Arithmetic Error

5 0x00000E 0x00008E Reserved

6 0x000010 0x000090 Reserved

7 0x000012 0x000092 Reserved