Datasheet

© 2005 Microchip Technology Inc. DS70043F-page 17
dsPIC30F
6.1 Interrupt Priority
Each interrupt source can be user assigned to one of 8
priority levels, 1 through 7. Levels 7 and 1 represent the
highest and lowest maskable priorities, respectively. A
priority level of 0 disables the interrupt.
Since more than one interrupt request source may be
assigned to a user specified priority level, a means is
provided to assign priority within a given level. This
method is called “Natural Order Priority.”
The Natural Order Priority of an interrupt is numerically
identical to its vector number. The natural order priority
scheme has 0 as the highest priority and 53 as the
lowest priority.
The ability for the user to assign every interrupt to one
of eight priority levels implies that the user can assign
a very high overall priority level to an interrupt with a
low natural order priority, thereby providing much
flexibility in designing applications that use a large
number of peripherals.
6.2 Interrupt Nesting
Interrupts, by default, are nestable. Any ISR that is in
progress may be interrupted by another source of
interrupt with a higher user assigned priority level.
Interrupt nesting may be optionally disabled by setting
the NSTDIS control bit (INTCON1<15>). When the
NSTDIS control bit is set, all interrupts in progress will
force the CPU priority to level 7 by setting IPL<2:0> =
111. This action will effectively mask all other sources
of interrupt until a RETFIE instruction is executed.
When interrupt nesting is disabled, the user assigned
interrupt priority levels will have no effect, except to
resolve conflicts between simultaneous pending
interrupts.
The IPL<2:0> bits become read-only when interrupt
nesting is disabled. This prevents the user software
from setting IPL<2:0> to a lower value, which would
effectively re-enable interrupt nesting.
36 0x00004C 0x0000CC IC3 – Input Capture 3
37 0x00004E 0x0000CE IC4 – Input Capture 4
38 0x000050 0x0000D0 IC5 – Input Capture 5
39 0x000052 0x0000D2 IC6 – Input Capture 6
40 0x000054 0x0000D4 OC5 – Output Compare 5
41 0x000056 0x0000D6 OC6 – Output Compare 6
42 0x000058 0x0000D8 OC7 – Output Compare 7
43 0x00005A 0x0000DA OC8 – Output Compare 8
44 0x00005C 0x0000DC INT3 – External Interrupt 3
45 0x00005E 0x0000DE INT4 – External Interrupt 4
46 0x000060 0x0000E0 CAN2
47 0x000062 0x0000E2 PWM – PWM Period Match
48 0x000064 0x0000E4 QEI – Position Counter Compare
49 0x000066 0x0000E6 DCI – Codec Transfer Done
50 0x000068 0x0000E8 LVD – Low Voltage Detect
51 0x00006A 0x0000EA FLTA – MCPWM FAULT A
52 0x00006C 0x0000EC FLTB – MCPWM FAULT B
53-61 0x00006E-0x00007E 0x00006E-0x00007E Reserved
TABLE 6-1: INTERRUPT VECTORS (CONTINUED)
Vector
Number
IVT Address AIVT Address Interrupt Source