Datasheet

dsPIC30F
DS70043F-page 8 © 2005 Microchip Technology Inc.
5.0 CPU ARCHITECTURE
5.1 Overview
The dsPIC30F CPU module has a 16-bit (data)
modified Harvard architecture with an enhanced
instruction set, including significant support for DSP.
The CPU has a 24-bit instruction word, with a variable
length opcode field. The Program Counter (PC) is 23
bits wide and addresses up to 4M x 24 bits of user
program memory space. The actual amount of program
memory implemented, as illustrated in Figure 5-1,
varies from one device to another. A single-cycle
instruction pre-fetch mechanism is used to help
maintain throughput and provides predictable
execution. All instructions execute in a single cycle,
with the exception of instructions that change the
program flow, the double-word move (MOV.D)
instruction and the table instructions. Overhead free
program loop constructs are supported using the DO
and REPEAT instructions, both of which are
interruptible at any point.
The dsPIC30F devices have sixteen 16-bit working
registers in the programmer’s model. Each of the
working registers can serve as a data, address or
address offset register. The 16th working register
(W15) operates as a software Stack Pointer for
interrupts and calls.
The dsPIC30F instruction set has two classes of
instructions: the MCU class of instructions and the DSP
class of instructions. These two instruction classes are
seamlessly integrated into the architecture and
execute from a single execution unit. The instruction
set includes many addressing modes and is designed
for optimum C compiler efficiency.
5.1.1 DATA MEMORY OVERVIEW
The data space can be addressed as 32 Kwords or 64
Kbytes and is split into two blocks, referred to as X and
Y data memory. Each memory block has its own
independent Address Generation Unit (AGU). The
MCU class of instructions operate solely through the X
memory AGU, which accesses the entire memory map
as one linear data space. Certain DSP instructions
operate through the X and Y AGUs to support dual
operand reads, which splits the data address space
into two parts. The X and Y data space boundary is
device specific.
The upper 32 Kbytes of the data space memory map
can optionally be mapped into program space at any
16K program word boundary defined by the 8-bit
Program Space Visibility Page (PSVPAG) register. The
program-to-data-space mapping feature lets any
instruction access program space as if it were data
space.
FIGURE 5-1: PROGRAM SPACE
MEMORY MAP
Reset – Target Address
User Memory
Space
000000
00007E
Reserved
000002
000080
Device Configuration
User Flash
Program Memory
018000
017FFE
Configuration Memory
Space
Data EEPROM
Osc. Fail Trap Vector
Address Error Trap Vector
Stack Error Trap Vector
Arithmetic Warn. Trap Vector
Reserved Vector
Reserved Vector
Interrupt Vector Table
(48K instructions)
(4 Kbytes)
800000
F80000
Registers
F8000E
F80010
FFFFFE
F7FFFE
Reserved
7FF000
7FEFFE
(Read 0’s)
000014
Vector
Reset – GOTO Instruction
000004
Reserved
7FFFFE
Reserved
000100
0000FE
000084
Alternate Vector Table
Reserved
Tab les
Reserved Vector