dsPIC30F Family Overview dsPIC® High-Performance 16-bit Digital Signal Controller © 2005 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
dsPIC30F dsPIC® High-Performance 16-bit Digital Signal Controller Family Overview Operating Range: On-Chip Flash, Data EEPROM and SRAM: • DC – 30 MIPS (30 MIPS @ 4.5-5.5V, -40 to 85°C) • Wide VDD range: 2.5-5.5V • Ind. (-40 to 85°C) and Ext. (-40 to 125°C) • Flash program memory: up to 144 Kbytes: - 10,000 erase/write cycles, min. (-40 to 85°C) - 100,000 erase/write cycles, typical • Data EEPROM: up to 4 Kbytes: - 100,000 erase/write cycles, min.
dsPIC30F Communication Modules: • 3-wire SPI™: up to 2 modules: - Framing supports I/O interface to simple codecs - Supports 8-bit and 16-bit data - Supports all serial clock formats and sampling modes • I2C™ full multi-master Slave mode support: - 7-bit and 10-bit addressing - Bus collision detection and arbitration • UART: up to 2 modules: - Interrupt-on-address bit detect - Wake-up on Start bit from Sleep mode - 4-character TX and RX FIFO buffers • Data Conversion Interface (DCI) module - Codec interface
dsPIC30F 1.0 dsPIC30F PRODUCT FAMILIES 1.1 General Purpose Family The dsPIC30F General Purpose Family (Table 1-1) is ideal for a wide variety of 16-bit MCU embedded applications. The variants with codec interfaces are well suited for audio applications. TABLE 1-1: dsPIC30F GENERAL PURPOSE FAMILY VARIANTS EEPROM Bytes Timer 16-bit Input Capture Output Compare Std. PWM Codec Interface A/D 12-bit 200 ksps UART SPI™ I2C™ CAN I/O Pins (Max.
dsPIC30F 1.3 Sensor Family The dsPIC30F Sensor Family products (Table 1-3) have features that support high-performance, low-cost embedded control applications. The 18- and 28-pin packages are designed to fit space-critical applications. SRAM Bytes EEPROM Bytes Timer 16-bit Input Capture Output Compare Std. PWM A/D 12-bit 200 Ksps UART SPI™ I2C™ I/O Pins (
dsPIC30F 2.0 dsPIC30F DEVICE FAMILY OVERVIEW The dsPIC30F device family employs a powerful 16-bit architecture that seamlessly integrates the control features of a microprocessor (MCU) with the computational capabilities of a digital signal processor (DSP). The resulting functionality is ideal for applications that rely on high-speed, repetitive computations as well as control.
dsPIC30F 3.0 DEVICE OVERVIEW FOR GENERAL PURPOSE AND SENSOR FAMILIES Note: The device depicted in Figure 3-1 is representative of this family. Other devices of the same family may vary in terms of number of pins and multiplexing of pin functions. Typically, smaller devices in the family contain a subset of the peripherals present in the device(s) shown here. Figure 3-1 shows a sample device block diagram typical of the dsPIC30F General Purpose Product Family.
dsPIC30F 4.0 DEVICE OVERVIEW FOR MOTOR CONTROL AND POWER CONVERSION FAMILY Note: The device depicted in Figure 4-1 is representative of this family. Other devices of the same family may vary in terms of number of pins and multiplexing of pin functions. Typically, smaller devices in the family contain a subset of the peripherals present in the device(s) shown here. Figure 4-1 shows a sample device block diagram typical of the dsPIC30F Motor Control Product Family.
dsPIC30F 5.1 Overview The dsPIC30F CPU module has a 16-bit (data) modified Harvard architecture with an enhanced instruction set, including significant support for DSP. The CPU has a 24-bit instruction word, with a variable length opcode field. The Program Counter (PC) is 23 bits wide and addresses up to 4M x 24 bits of user program memory space. The actual amount of program memory implemented, as illustrated in Figure 5-1, varies from one device to another.
dsPIC30F 5.1.2 ADDRESSING MODES OVERVIEW Overhead free circular buffers (modulo addressing) are supported in both X and Y address spaces. The modulo addressing removes the software boundary checking overhead for DSP algorithms. Furthermore, the X AGU circular addressing can be used with any of the MCU class of instructions. The X AGU also supports bit-reversed addressing to greatly simplify input or output data reordering for radix-2 FFT algorithms.
dsPIC30F 5.2 Programmer’s Model The programmer’s model, shown in Figure 5-2, consists of 16 x 16-bit working registers (W0 through W15), 2 x 40-bit accumulators (ACCA and ACCB), STATUS Register (SR), Data Table Page register (TBLPAG), Program Space Visibility Page register (PSVPAG), DO and REPEAT registers (DOSTART, DOEND, DCOUNT and RCOUNT) and Program Counter (PC). The working registers can act as data, address or offset registers. All registers are memory mapped.
dsPIC30F FIGURE 5-2: PROGRAMMER’S MODEL 15 Legend: 0 W0/WREG DIV and MUL Result Registers PUSH.
dsPIC30F 5.3 Data Address Space The core has two data spaces, X and Y. These data spaces can be considered either separate (for some DSP instructions), or as one unified linear address range (for MCU instructions). The data spaces are accessed using two Address Generation Units (AGUs) and separate data paths.
dsPIC30F FIGURE 5-3: SAMPLE DATA SPACE MEMORY MAP MS Byte Address MSB 2 Kbyte SFR Space 0x0001 LS Byte Address 16-bits LSB SFR Space 0x0000 0x07FE 0x0800 0x07FF 0x0801 X Data RAM (X) 8 Kbyte SRAM Space 0x17FF 0x1801 0x17FE 0x1800 Y Data RAM (Y) 8 Kbyte SRAM boundary 0x27FF 0x27FE 0x2801 0x2800 0x8001 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFF © 2005 Microchip Technology Inc.
dsPIC30F 5.4 DSP Engine The DSP engine consists of a high-speed, single-cycle, 17-bit x 17-bit multiplier, a barrel shifter and a 40-bit adder/subtractor with two target accumulators, round and saturation logic, all of which enable efficient execution of computationally intensive DSP algorithms. The 17-bit x 17-bit multiplier is also utilized for MCUbased multiply instructions.
dsPIC30F FIGURE 5-4: DSP ENGINE BLOCK DIAGRAM 40 S a 40 Round t 16 u Logic r a t e 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Enable Negate 40 40 40 Barrel Shifter 16 X Data Bus 40 Y Data Bus Sign-Extend 32 16 Zero Backfill 32 33 17-bit Multiplier/Scaler Operand Latches 16 16 To/From W Array © 2005 Microchip Technology Inc.
dsPIC30F 6.0 EXCEPTION PROCESSING The dsPIC30F has four processor exceptions (traps) and up to 45 sources of interrupts, which must be arbitrated based on a priority scheme. The processor core is responsible for reading the Interrupt Vector Table (IVT) and transferring the address contained in the interrupt vector to the program counter. The Interrupt Vector Table (IVT) and Alternate Interrupt Vector Table (AIVT) are placed near the beginning of program memory (0x000004) for ease of debugging.
dsPIC30F TABLE 6-1: INTERRUPT VECTORS (CONTINUED) Vector Number IVT Address AIVT Address 36 0x00004C 0x0000CC 37 0x00004E 0x0000CE IC4 – Input Capture 4 38 0x000050 0x0000D0 IC5 – Input Capture 5 39 0x000052 0x0000D2 IC6 – Input Capture 6 40 0x000054 0x0000D4 OC5 – Output Compare 5 41 0x000056 0x0000D6 OC6 – Output Compare 6 42 0x000058 0x0000D8 OC7 – Output Compare 7 IC3 – Input Capture 3 43 0x00005A 0x0000DA OC8 – Output Compare 8 44 0x00005C 0x0000DC INT3 – Externa
dsPIC30F 6.3 Traps Traps can be considered as non-maskable, nestable interrupts that adhere to a fixed priority structure. Traps are intended to provide the user a means to correct erroneous operation during debug and when operating within the application. If the user does not intend to take corrective action in the event of a trap error condition, these vectors must be loaded with the address of a software routine that will reset the device.
dsPIC30F 7.0 SYSTEM INTEGRATION System management services provided by the dsPIC30F device family include: • • • • • • • • Control of clock options and oscillators Power-on Reset Programmable Brown-out Reset Program control of Power-up Timer Oscillator start-up timer/stabilizer Watchdog Timer with RC oscillator Fail-Safe Clock Monitor Reset by multiple sources 7.1 Clock Options and Oscillators There are three primary clock oscillators: XTL, XT and HS.
dsPIC30F FIGURE 7-1: OSC1 OSC2 OSCILLATOR SYSTEM BLOCK DIAGRAM Primary Oscillator PLL x4, x8, x16 PLL Primary Osc Internal Fast RC (FRC) Oscillator Secondary Osc SOSCO SOSCI Secondary Oscillator 32 kHz Clock Switching and Control Block FOSC Programmable 4 x FCY Clock Divider Internal Low Power RC (LPRC) Osc To Timer1 7.4 Programmable Power-up Timer (PWRT) There are two internal timers that offer necessary delays on power-up.
dsPIC30F 7.6 Watchdog Timer (WDT) The primary function of the Watchdog Timer (WDT) is to reset the processor in the event of a software malfunction. The WDT is a free running timer that runs off an on-chip RC oscillator, requiring no external component. The WDT Timer continues to operate even if the main processor clock (e.g., the crystal oscillator) fails.
dsPIC30F 8.0 DEVICE POWER MANAGEMENT Power management services dsPIC30F device include: FIGURE 8-1: provided by External LVD Input pin the VDD Real-Time Clock Source Switching Configuration bits determine the clock source upon Power-on Reset (POR) and Brown-out Reset (BOR). Thereafter, the clock source can be changed between permissible clock sources. The OSCCON register controls the clock switching and reflects system clock related Status bits.
dsPIC30F 8.3 Power-Saving Modes The dsPIC30F devices have two reduced power modes that can be entered through execution of the PWRSAV instruction. • Sleep mode: The CPU, system clock source and any peripherals that operate on the system clock source are disabled. This is the lowest power mode of the device. • Idle mode: The CPU is disabled, but the system clock source continues to operate. Peripherals continue to operate, but can optionally be disabled.
dsPIC30F 9.0 dsPIC30F PERIPHERALS The Digital Signal Controller (DSC) family of 16-bit MCU devices provides the integrated functionality of many peripherals.
dsPIC30F 9.2 General Purpose Timer Modules Further, the following operational characteristics are supported: The General Purpose (GP) Timer modules provide the time base elements for Input Capture and Output Compare/PWM. They can be configured for real-time clock operation as well as various timer/counter modes. The timer modes count pulses of the internal time base, whereas counter modes count external pulses that appear on the Timer Clock pin.
dsPIC30F 9.2.2 TIMER 2/3 9.3 Motor Control PWM Module The Timer2/3 module is a 32-bit timer (which can be configured as two 16-bit timers) with selectable operating modes. These timers are used by other peripheral modules, such as: The Motor Control PWM (MCPWM) module simplifies the task of generating multiple, synchronized pulse width modulated outputs.
dsPIC30F FIGURE 9-2: 8-OUTPUT PWM MODULE BLOCK DIAGRAM PWMCON1 PWM Enable and Mode SFRs PWMCON2 DTCON1 Dead-Time Control SFRs DTCON2 FLTACON Fault Pin Control SFRs FLTBCON OVDCON PWM Manual Control SFR PWM Generator #4 16-bit Data Bus PDC4 Buffer PDC4 Comparator PWM Generator #3 PTMR Channel 3 Dead-Time Generator and Override Logic Comparator PWM Generator #2 PTPER PWM Generator #1 PTPER Buffer PWM4H Channel 4 Dead-Time Generator and Override Logic PWM4L PWM3H Output Driver PWM3L Block
dsPIC30F 9.3.2 PWM TIME BASE The PWM time base is provided by a 15-bit timer with a prescaler and postscaler. The PWM time base can be configured for four different modes of operation: • • • • Free Running mode Single-Shot mode Continuous Up/Down Count mode Continuous Up/Down Count mode with interrupts for double-updates TABLE 9-1: The Up/Down Counting modes support center aligned PWM generation.
dsPIC30F FIGURE 9-3: QUADRATURE ENCODER INTERFACE BLOCK DIAGRAM TQCKPS<1:0> Sleep Input TQCS TCY Synchronize 0 Det 1 2 Prescaler 1, 8, 64, 256 1 QEIM<2:0> 0 TQGATE QEA Programmable Digital Filter UPDN_SRC 0 QEICON<11> 2 Quadrature Encoder Interface Logic QEB Programmable Digital Filter INDX Programmable Digital Filter Q CK Q QEIIF Event Flag 16-bit Up/Down Counter (POSCNT) Reset Comparator/ Zero Detect Equal 3 QEIM<2:0> Mode Select 1 D Max Count Register (MAXCNT) 3 PCDOUT Existi
dsPIC30F 9.5 Input Capture Module The Input Capture module is useful in applications requiring Frequency (Period) and Pulse measurement. The dsPIC30F devices support up to eight input capture channels. The Input Capture module captures the 16-bit value of the selected time base register when an event occurs at the ICx pin. The events that cause a capture event are listed below in three categories: 1. 2. 3.
dsPIC30F FIGURE 9-4: DCI MODULE BLOCK DIAGRAM BCG Control Bits CSCKD FOSC/4 Sample Rate Generator CSCK COFSD Word Size Selection bits 16-bit Data Bus Frame Length Selection bits DCI Mode Selection bits Frame Synchronization Generator COFS Receive Buffer Registers w/Shadow DCI Buffer Control Unit 15 Transmit Buffer Registers w/Shadow 0 DCI Shift Register CSDI CSDO 9.
dsPIC30F 9.9 UART Module The UART is a full-duplex asynchronous system that can communicate with peripheral devices, such as personal computers, RS-232, and RS-485 interfaces. The dsPIC30F devices have one or more UART’s. The key features of the UART module are: • • • • • • • • • • • • • Full-duplex operation with 8- or 9-bit data Even, Odd or No Parity options (for 8-bit data) One or two Stop bits Fully integrated Baud Rate Generator with 16-bit prescaler Baud rates range from up to 2.
dsPIC30F 9.12 I/O Pins Some pins for the I/O pin functions are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. All I/O port pins have three registers directly associated with the operation of the port pin. The Data Direction register determines whether the pin is an input or an output. The Port Data Latch register provides latched output data for the I/O pins.
dsPIC30F 10.0 dsPIC30F INSTRUCTION SET 10.2.1 10.1 Introduction As the instruction summary tables show, most instructions execute in a single cycle, with the following exceptions: The dsPIC30F instruction set provides a broad suite of instructions, which supports traditional microcontroller applications, and a class of instructions, which supports math intensive applications.
dsPIC30F TABLE 10-2: SYMBOLS USED IN SUMMARY TABLES Symbol Description # Literal operand designation Acc Accumulator A or Accumulator B AWB Accumulator Write Back bit4 4-bit wide bit position (0:15) Expr Absolute address, label or expression (resolved by the linker) f File register address lit1 1-bit literal (0:1) lit4 4-bit literal (0:15) lit5 5-bit literal (0:31) lit8 8-bit literal (0:255) lit10 10-bit literal (0:255 for Byte mode, 0:1023 for Word mode) lit14 14-bit literal (0:1
dsPIC30F TABLE 10-3: MOVE INSTRUCTIONS Assembly Syntax EXCH Wns,Wnd MOV MOV Description Words Cycles Swap Wns and Wnd 1 1 f {,WREG} Move f to destination 1 1 WREG,f Move WREG to f 1 1 MOV f,Wnd Move f to Wnd 1 1 MOV Wns,f Move Wns to f 1 1 MOV.
dsPIC30F TABLE 10-4: Assembly MATH INSTRUCTIONS Syntax Description Words Cycles ADD ADD ADD ADD ADDC ADDC ADDC ADDC DAW.B DEC DEC DEC2 DEC2 DIV.S DIV.SD DIV.U DIV.UD DIVF INC INC INC2 INC2 MUL MUL.SS MUL.SU MUL.SU MUL.US MUL.UU MUL.
dsPIC30F TABLE 10-5: LOGIC INSTRUCTIONS Assembly Syntax AND f {,WREG} Destination = f .AND. WREG AND #lit10,Wn Wn = lit10 .AND. Wn 1 1 AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 CLR f f = 0x0000 1 1 CLR WREG WREG = 0x0000 1 1 CLR Wd Wd = 0x0000 1 1 COM f {,WREG} Destination = f 1 1 COM Ws,Wd Wd = Ws 1 1 IOR f {,WREG} Destination = f .IOR. WREG 1 1 IOR #lit10,Wn Wn = lit10 .IOR. Wn 1 1 IOR Wb,#lit5,Wd Wd = Wb .IOR.
dsPIC30F TABLE 10-6: ROTATE/SHIFT INSTRUCTIONS Assembly Syntax ASR f {,WREG} Destination = arithmetic right shift f ASR Ws,Wd Wd = arithmetic right shift Ws 1 1 ASR Wb,#lit4,Wnd Wnd = arithmetic right shift Wb by lit4 1 1 ASR Wb,Wns,Wnd Wnd = arithmetic right shift Wb by Wns 1 1 LSR f {,WREG} Destination = logical right shift f 1 1 LSR Ws,Wd Wd = logical right shift Ws 1 1 LSR Wb,#lit4,Wnd Wnd = logical right shift Wb by lit4 1 1 LSR Wb,Wns,Wnd Wnd = logical right shif
dsPIC30F TABLE 10-8: COMPARE/SKIP INSTRUCTIONS Assembly Syntax Description Words Cycles BTSC f,#bit4 Bit test f, skip if clear 1 1 (2 or 3) BTSC Ws,#bit4 Bit test Ws, skip if clear 1 1 (2 or 3) BTSS f,#bit4 Bit test f, skip if set 1 1 (2 or 3) BTSS Ws,#bit4 Bit test Ws, skip if set 1 1 (2 or 3) CP f Compare (f – WREG) 1 1 CP Wb,#lit5 Compare (Wb – lit5) 1 1 CP Wb,Ws Compare (Wb – Ws) 1 1 CP0 f Compare (f – 0x0000) 1 1 CP0 Ws Compare (Ws – 0x0000) 1 1 CPB f
dsPIC30F TABLE 10-9: PROGRAM FLOW INSTRUCTIONS Assembly Syntax BRA Expr Branch unconditionally BRA Wn Computed branch 1 2 BRA C,Expr Branch if Carry (no Borrow) 1 1 (2) BRA GE,Expr Branch if greater than or equal 1 1 (2) BRA GEU,Expr Branch if unsigned greater than or equal 1 1 (2) BRA GT,Expr Branch if greater than 1 1 (2) BRA GTU,Expr Branch if unsigned greater than 1 1 (2) BRA LE,Expr Branch if less than or equal 1 1 (2) BRA LEU,Expr Branch if unsigned less tha
dsPIC30F TABLE 10-10: SHADOW/STACK INSTRUCTIONS Assembly Syntax LNK #lit14 POP POP POP.D Words Cycles Link Frame Pointer 1 1 f Pop TOS to f 1 1 Wd Pop TOS to Wd 1 1 Wnd Double pop from TOS to Wnd:Wnd + 1 1 2 Pop shadow registers 1 1 POP.S Description PUSH f Push f to TOS 1 1 PUSH Ws Push Ws to TOS 1 1 PUSH.D Wns Push double Wns:Wns + 1 to TOS 1 2 PUSH.
dsPIC30F 11.0 MICROCHIP DEVELOPMENT TOOL SUPPORT Microchip offers comprehensive development tools and libraries to support the dsPIC30F architecture. In addition, the company is partnering with many third TABLE 11-1: dsPIC30F DEVELOPMENT TOOLS Development Tool Essential Software Tools party tools manufacturers for additional dsPIC30F device support. Table 11-1 lists development tools that support the dsPIC30F family. The paragraphs that follow describe each of the tools in more detail.
dsPIC30F 11.1 MPLAB® Integrated Development Environment V6.XX Software The MPLAB Integrated Development Environment (IDE) is available at no cost. The MPLAB IDE lets you edit, compile and emulate from a single user interface, as depicted in Figure 11-1. You can design and develop code for the dsPIC devices in the same design environment as PICmicro microcontrollers.
dsPIC30F 11.2 MPLAB ASM30 Assembler/Linker/ Librarian MPLAB ASM30 is a full-featured Macro Assembler. User-defined macros, conditional assembly and a variety of assembler directives make the MPLAB ASM30 a powerful code generation tool. The accompanying MPLAB LINK30 Linker and MPLAB LIB30 Librarian modules allow efficient linking, library creation and maintenance.
dsPIC30F 11.5 MPLAB C30 Compiler/Linker/ Librarian The MPLAB C30 has these characteristics: • 16-bit native data types • Efficient use of register based, 3-operand instructions • Complex addressing modes • Efficient multi-bit shift operations • Efficient signed/unsigned comparisons The Microchip Technology MPLAB C30 provides C language support for the dsPIC30F family. This C compiler is a fully ANSI compliant product with standard libraries.
dsPIC30F 11.6 MPLAB ICD 2 In-Circuit Debugger The MPLAB ICD 2 In-Circuit Debugger is a powerful, low cost, run-time development tool that uses in-circuit debugging capability built into the dsPIC30F Flash devices. This feature, along with Microchip’s In-Circuit Serial ProgrammingTM protocol, gives you cost effective, in-circuit debugging from the graphical user interface of MPLAB.
dsPIC30F 11.8 PRO MATE® II Universal Device Programmer The PRO MATE II universal device programmer is a full-featured, CE-compliant programming tool, capable of operating in both stand-alone and PC-hosted modes. The PRO MATE II universal device programmer has programmable VDD and VPP supplies, which allow it to verify programmed memory at VDDMIN and VDDMAX for maximum reliability.
dsPIC30F 12.0 dsPIC30F DEVELOPMENT TOOLS AND APPLICATION LIBRARIES Microchip offers a comprehensive set of tools and libraries to help with rapid development of dsPIC30F based application(s). Also, Microchip partners with key third party tool manufacturers to develop quality hardware and software tools in support of the dsPIC30F product family.
dsPIC30F 12.1 TABLE 12-2: Math Library The dsPIC30F Math Library is the compiled version of the math library that is distributed with the highly optimized, ANSI-compliant dsPIC30F MPLAB® C30 compiler (SW006012). It contains advanced single and double-precision floating-point arithmetic and trigonometric functions from the standard C header file . The library delivers small program code size and data size, reduced cycles and high accuracy.
dsPIC30F 12.2 Peripheral Driver Library 12.3 DSP Algorithm Library Microchip offers a free peripheral driver library that supports the setup and control of dsPIC30F hardware peripherals, including, but not limited to: The free DSP library supports multiple filtering, convolution, vector and matrix functions.
dsPIC30F TABLE 12-4: FUNCTION EXECUTION TIMES Function Cycle Count Equation Conditions(1) Number of Cycles(2) Execution Time @30 MIPS Complex FFT(3) - N=64 3739 124.6 μs (3) - N=128 8485 282.8 μs Complex FFT(3) - N=256 19055 635.2 μs Block FIR 53+N(4+M) N=32, M=32 1205 40.2 μs Block FIR Lattice 41+N(4+7M) N=32, M=32 7337 244.6 μs Complex FFT Block IIR Canonic Block IIR Lattice Matrix Add Matrix Transpose 36+N(8+7S) N=32, S=4 1188 39.
dsPIC30F 12.4.2 DIGITAL SIGNAL PROCESSING (DSP) AND ARITHMETIC OPERATIONS: dsPICworks Data Analysis and DSP Software has a wide range of DSP and arithmetic functions that can be applied to signals. Standard DSP functions include transform operations – FFT and DCT, convolution and correlation, signal decimation, signal interpolation sample rate conversion and digital filtering. Digital filtering is an important part of dsPICworks.
dsPIC30F • The following window functions are supported: - Rectangular - Hanning (Hann) - Hamming - Triangular - Blackman - Exact Blackman - 3 Term Cosine - 3 Term Cosine with continuous 3rd Derivative - Minimum 3 Term Cosine - 4 Term Cosine - 4 Term Cosine with continuous 5th Derivative - Minimum 4 Term Cosine - Good 4 Term Blackman Harris - Harris Flat Top - Kaiser - Dolph-Tschebyscheff - Taylor - Gaussian • Reports show design details such as window coefficients and Impulse Response prior to multiplying
dsPIC30F CMX-RTX allows a task of higher priority that is able to run (whether starting or resuming) to preempt the running task. The scheduler saves the context of the running (lower priority) task and restores the context of the higher priority task so that it is now running. A truly preemptive RTOS allows interrupts to cause an immediate task switch, which means that the interrupts now have the added ability of using the RTOS’s functions.
dsPIC30F Key features of the CMX-Tiny+™ for dsPIC30F include: • • • • • • • • • Extremely small Flash/RAM footprint Truly preemptive RTOS Low-Power mode supported Full source code with every purchase Free technical support and updates Low, economical pricing No royalties on shipped products Backward compatible with CMX-Scheduler™ Integrated with CMX-MicroNet™ for optional networking connectivity 12.6.3 CMX-SCHEDULER™ CMX-Scheduler is the result of a special collaboration between CMX and Microchip.
dsPIC30F Supported Protocols 12.8 • • • • • • • • • • Microchip offers V.22/V.22bis (1200/2400 bps) and V.32/V.32bis (9600/14400 bps) ITU-T specifications to support a range of “connected” applications.
dsPIC30F 12.10 OSEK Operating Systems The dsPIC30F product family supports Operating Systems for the OSEK/VDX vehicle software standard. The functionality of OSEK “Offene Systeme und deren Schnittstellen für die Elektronik im Kraftfahrzeug” (open systems and the corresponding interfaces for automotive electronics) is harmonized with VDX “Vehicle Distributed eXecutive” yielding OSEK/VDX. Microchip also provides Internal and External CAN driver support.
dsPIC30F 13.0 dsPIC30F HARDWARE DEVELOPMENT BOARDS Microchip provides several hardware development boards that help you quickly prototype and validate key design requirements. Each board features key TABLE 13-1: HARDWARE DEVELOPMENT BOARDS Development Tool Development Boards and Reference Designs dsPIC30F peripherals and supports Microchip’s MPLAB In-Circuit Debugger (ICD 2) tool for cost effective debugging and programming of the dsPIC30F device. These boards are shown in Table13-1.
dsPIC30F 13.1 dsPICDEM™ 80-Pin Starter Development Board This development board offers a very economical way to evaluate both the dsPIC30F and dsPIC33F General Purpose and Motor Control Family devices. This board is an ideal prototyping tool to help you quickly develop and validate key design requirements.
dsPIC30F 13.3 dsPICDEM 1.1 Development Board The dsPICDEM 1.1 Development Board is a low cost development tool that lets you familiarize yourself with the dsPIC30F 16-bit architecture, high performance peripherals and powerful instruction set. This development board is an ideal prototyping tool to help you quickly develop and validate key design requirements. Some key features and attributes of the dsPICDEM 1.
dsPIC30F FIGURE 13-4: dsPIC30F MOTOR CONTROL DEVELOPMENT SYSTEM • • • • • • • • • • In-Circuit Debugger interface (MPLAB ICD 2) ICE 4000 Emulator interface Microchip temperature sensor Microchip Dual Channel Digital Potentiometer 2x16 LCD General purpose prototyping area Various LEDs, switches and potentiometers External 64K x 16 SRAM External EE memory for storing HTML pages Expansion header for user applications The connectivity development board is shipped with a 9V power supply, RS-232 I/O cable, pr
dsPIC30F APPENDIX A: TABLE A-1: DEVICE I/O PINOUTS AND FUNCTIONS FOR GENERAL PURPOSE AND SENSOR FAMILY Table A-1 provides a brief description of device I/O pinouts and functions that can be multiplexed to a port pin. Multiple functions may exist on one port pin. When multiplexing occurs, the peripheral module’s functional requirements may force an override of the data direction of the port pin.
dsPIC30F TABLE A-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Type Input Buffer Type PGD PGC I/O I ST ST In-Circuit Serial Programming data input/output pin. In-Circuit Serial Programming clock input pin. RA6-RA7 RA9-RA10 RA12-RA15 I/O I/O I/O ST ST ST PORTA is a bidirectional I/O port. Pin Name Description RB0-RB15 I/O ST PORTB is a bidirectional I/O port. RC1-RC4 RC13-RC15 I/O I/O ST ST PORTC is a bidirectional I/O port. RD0-RD15 I/O ST PORTD is a bidirectional I/O port.
dsPIC30F Pin Diagrams MCLR AN0/VREF+/CN2/RB0 AN1/VREF-/CN3/RB1 AN2/SS1/LVDIN/CN4/RB2 AN3/CN5/RB3 OSC1/CLKI OSC2/CLKO/RC15 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 1 2 3 4 5 6 7 8 9 dsPIC30F3012 dsPIC30F2011 18-Pin PDIP and SOIC 18 17 16 15 14 13 12 11 10 AVDD AVSS AN6/SCK1/INT0/OCFA/RB6 EMUD2/AN7/OC2/IC2/RB7 VDD VSS PGC/EMUC/AN5/U1RX/SDI1/SDA/CN7/RB5 PGD/EMUD/AN4/U1TX/SDO1/SCL/CN6/RB4 EMUC2/OC1/IC1/INT1/RD0 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AVDD AVSS AN6/OCFA/RB6 EMUD2/
dsPIC30F Pin Diagrams (Continued) MCLR AN0/VREF+/CN2/RB0 AN1/VREF-/CN3/RB1 AN2/SS1/LVDIN/CN4/RB2 AN3/CN5/RB3 AN4/CN6/RB4 AN5/CN7/RB5 PGC/EMUC/AN6/OCFA/RB6 PGD/EMUD/AN7/RB7 AN8/RB8 VDD VSS OSC1/CLKI OSC2/CLKO/RC15 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 INT0/RA11 IC2/INT2/RD9 RD3 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 dsPIC30F3014 40-Pin PDIP 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 AVDD AVSS AN9/RB9 AN10/RB10 AN11/RB11 AN12/RB12 EMUC2/OC1/RD0 E
dsPIC30F Pin Diagrams (Continued) 44 43 42 41 40 39 38 37 36 35 34 AN3/CN5/RB3 AN2/SS1/LVDIN/CN4/RB2 AN1/VREF-/CN3/RB1 AN0/VREF+/CN2/RB0 MCLR NC AVDD AVSS AN9/RB9 AN10/RB10 AN11/RB11 44-Pin TQFP dsPIC30F3014 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 AN12/RB12 EMUC2/OC1/RD0 EMUD2/OC2/RD1 VDD VSS NC RF0 RF1 U2RX/RF4 U2TX/RF5 U1RX/SDI1/SDA/RF2 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 INT0/RA11 IC2/INT2/RD9 RD3 VSS NC VDD RD2 IC1/INT1/RD8 EMUC3/SCK1/RF6 EMUD3/U1TX
dsPIC30F Pin Diagrams (Continued) 44 43 42 41 40 39 38 37 36 35 34 AN3/CN5/RB3 AN2/SS1/LVDIN/CN4/RB2 AN1/VREF-/CN3/RB1 AN0/VREF+/CN2/RB0 MCLR NC AVDD AVSS AN9/CSCK/RB9 AN10/CSDI/RB10 AN11/CSDO/RB11 44-Pin TQFP dsPIC30F4013 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 AN12/COFS/RB12 EMUC2/OC1/RD0 EMUD2/OC2/RD1 VDD VSS NC C1RX/RF0 C1TX/RF1 U2RX/RF4 U2TX/RF5 U1RX/SDI1/SDA/RF2 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 INT0/RA11 IC2/INT2/RD9 OC4/RD3 VSS NC VDD OC3/RD2
dsPIC30F Pin Diagrams (Continued) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 CSDO/RG13 CSDI/RG12 CSCK/RG14 C2RX/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VDD VSS OC8/CN16/RD7 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 EMUD2/OC2/RD1 64-Pin TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dsPIC30F5011 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 EMUC1/SOSCO/T1CK/CN0/RC14 EMUD1/SOSCI/T4CK/CN1/RC13 EMUC2/OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/INT2/RD9 IC1/INT1/RD8 VSS OSC2/CLKO/RC15 OSC1/CLK
dsPIC30F Pin Diagrams (Continued) IC5/RD12 OC4/RD3 OC3/RD2 EMUD2/OC2/RD1 OC6/CN14/RD5 OC5/CN13/RD4 IC6/CN19/RD13 OC7/CN15/RD6 C2RX/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VDD VSS OC8/CN16/RD7 CSCK/RG14 RA7/CN23 RA6/CN22 CSDI/RG12 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 CSDO/RG13 80-Pin TQFP COFS/RG15 T2CK/RC1 60 EMUC1/SOSCO/T1CK/CN0/RC14 59 EMUD1/SOSCI/CN1/RC13 58 EMUC2/OC1/RD0 57 5 56 IC4/RD11 IC3/RD10 6 55 IC2/RD9 7 54 IC1/RD8 8 53 INT4/RA15 9 52 INT3/RA14 VSS 1
dsPIC30F Pin Diagrams (Continued) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RG13 RG12 RG14 C2RX/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VDD VSS OC8/CN16/RD7 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 EMUD2/OC2/RD1 64-Pin TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dsPIC30F6011A 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 EMUC1/SOSCO/T1CK/CN0/RC14 EMUD1/SOSCI/T4CK/CN1/RC13 EMUC2/OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/INT2/RD9 IC1/INT1/RD8 VSS OSC2/CLKO/RC15 OSC1/CLKI VDD SCL/RG2
dsPIC30F Pin Diagrams (Continued) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 CSDO/RG13 CSDI/RG12 CSCK/RG14 C2RX/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VDD VSS OC8/CN16/RD7 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 EMUD2/OC2/RD1 64-Pin TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dsPIC30F6012A 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 EMUC1/SOSCO/T1CK/CN0/RC14 EMUD1/SOSCI/T4CK/CN1/RC13 EMUC2/OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/INT2/RD9 IC1/INT1/RD8 VSS OSC2/CLKO/RC15 OSC1/CL
dsPIC30F Pin Diagrams (Continued) IC5/RD12 OC4/RD3 OC3/RD2 EMUD2/OC2/RD1 OC6/CN14/RD5 OC5/CN13/RD4 IC6/CN19/RD13 OC8/CN16/RD7 OC7/CN15/RD6 C1TX/RF1 C1RX/RF0 VDD VSS C2RX/RG0 C2TX/RG1 RG14 CN23/RA7 CN22/RA6 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 RG13 RG12 80-Pin TQFP RG15 T2CK/RC1 1 2 60 EMUC1/SOSCO/T1CK/CN0/RC14 59 EMUD1/SOSCI/CN1/RC13 58 EMUC2/OC1/RD0 57 IC4/RD11 IC3/RD10 T3CK/RC2 3 T4CK/RC3 T5CK/RC4 4 5 56 SCK2/CN8/RG6 6 55 IC2/RD9 SDI2/CN9/RG7 7 54 IC
dsPIC30F Pin Diagrams (Continued) IC5/RD12 OC4/RD3 OC3/RD2 EMUD2/OC2/RD1 OC6/CN14/RD5 OC5/CN13/RD4 IC6/CN19/RD13 OC8/CN16/RD7 OC7/CN15/RD6 C1TX/RF1 C1RX/RF0 VDD VSS C2RX/RG0 C2TX/RG1 CSCK/RG14 CN23/RA7 CN22/RA6 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 CSDO/RG13 CSDI/RG12 80-Pin TQFP COFS/RG15 T2CK/RC1 1 2 60 EMUC1/SOSCO/T1CK/CN0/RC14 59 EMUD1/SOSCI/CN1/RC13 58 EMUC2/OC1/RD0 57 56 IC4/RD11 IC3/RD10 T3CK/RC2 3 T4CK/RC3 T5CK/RC4 SCK2/CN8/RG6 4 6 55 IC2/RD9 SDI2/CN9
dsPIC30F Pin Diagrams (Continued) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RG13 RG12 RG14 C2RX/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VDD VSS OC8/CN16/RD7 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 EMUD2/OC2/RD1 64-Pin TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dsPIC30F6011* 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 EMUC1/SOSCO/T1CK/CN0/RC14 EMUD1/SOSCI/T4CK/CN1/RC13 EMUC2/OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/INT2/RD9 IC1/INT1/RD8 VSS OSC2/CLKO/RC15 OSC1/CLKI VDD SCL/RG2
dsPIC30F Pin Diagrams (Continued) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 CSDO/RG13 CSDI/RG12 CSCK/RG14 C2RX/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VDD VSS OC8/CN16/RD7 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 EMUD2/OC2/RD1 64-Pin TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dsPIC30F6012* 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 EMUC1/SOSCO/T1CK/CN0/RC14 EMUD1/SOSCI/T4CK/CN1/RC13 EMUC2/OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/INT2/RD9 IC1/INT1/RD8 VSS OSC2/CLKO/RC15 OSC1/CL
dsPIC30F Pin Diagrams (Continued) IC5/RD12 OC4/RD3 OC3/RD2 EMUD2/OC2/RD1 OC6/CN14/RD5 OC5/CN13/RD4 IC6/CN19/RD13 OC7/CN15/RD6 C2RX/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VDD VSS OC8/CN16/RD7 RG14 RA7/CN23 RA6/CN22 RG12 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 RG13 80-Pin TQFP RG15 1 T2CK/RC1 2 60 EMUC1/SOSCO/T1CK/CN0/RC14 59 EMUD1/SOSCI/CN1/RC13 58 EMUC2/OC1/RD0 57 56 IC4/RD11 IC3/RD10 T3CK/RC2 3 T4CK/RC3 T5CK/RC4 4 SCK2/CN8/RG6 6 55 IC2/RD9 7 54 IC1/RD8 8 53 IN
dsPIC30F Pin Diagrams (Continued) IC5/RD12 OC4/RD3 OC3/RD2 EMUD2/OC2/RD1 OC6/CN14/RD5 OC5/CN13/RD4 IC6/CN19/RD13 OC7/CN15/RD6 C2RX/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VDD VSS OC8/CN16/RD7 CSCK/RG14 RA7/CN23 RA6/CN22 CSDI/RG12 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 CSDO/RG13 80-Pin TQFP COFS/RG15 T2CK/RC1 60 EMUC1/SOSCO/T1CK/CN0/RC14 59 EMUD1/SOSCI/CN1/RC13 58 EMUC2/OC1/RD0 57 5 56 IC4/RD11 IC3/RD10 6 55 IC2/RD9 7 54 IC1/RD8 8 53 INT4/RA15 9 52 INT3/RA14 VSS 1
dsPIC30F APPENDIX B: TABLE B-1: DEVICE I/O PINOUTS AND FUNCTIONS FOR MOTOR CONTROL FAMILY PINOUT I/O DESCRIPTIONS FOR MOTOR CONTROL FAMILY Pin Type Buffer Type AN0-AN15 I Analog Pin Name Table B-1 provides a brief description of device I/O pinouts and the functions that may be multiplexed to a port pin. Multiple functions may exist on one port pin. When multiplexing occurs, the peripheral module’s functional requirements may force an override of the data direction of the port pin.
dsPIC30F TABLE B-1: PINOUT I/O DESCRIPTIONS FOR MOTOR CONTROL FAMILY (CONTINUED) Pin Type Buffer Type FLTA FLTB PWM1L PWM1H PWM2L PWM2H PWM3L PWM3H PWM4L PWM4H I I O O O O O O O O ST ST — — — — — — — — PWM Fault A input. PWM Fault B input. PWM 1 Low output. PWM 1 High output. PWM 2 Low output. PWM 2 High output. PWM 3 Low output. PWM 3 High output. PWM 4 Low output. PWM 4 High output. MCLR I/P ST Master Clear (Reset) input or programming voltage input.
dsPIC30F TABLE B-1: PINOUT I/O DESCRIPTIONS FOR MOTOR CONTROL FAMILY (CONTINUED) Pin Type Buffer Type U1RX U1TX U1ARX U1ATX U2RX U2TX I O I O I O ST — ST — ST — UART1 Receive. UART1 Transmit. UART1 Alternate Receive. UART1 Alternate Transmit. UART2 Receive. UART2 Transmit. VDD P — Positive supply for logic and I/O pins. VSS P — Ground reference for logic and I/O pins. VREF+ I Analog Analog Voltage Reference (High) input. VREF- I Analog Analog Voltage Reference (Low) input.
dsPIC30F Pin Diagrams (Continued) MCLR EMUD3/AN0/VREF+/CN2/RB0 EMUC3/AN1/VREF-/CN3/RB1 AN2/SS1/LVDIN/CN4/RB2 AN3/INDX/CN5/RB3 AN4/QEA/IC7/CN6/RB4 AN5/QEB/IC8/CN7/RB5 AN6/OCFA/RB6 AN7/RB7 AN8/RB8 VDD VSS OSC1/CLKI OSC2/CLKO/RC15 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 FLTA/INT0/RE8 EMUD2/OC2/IC2/INT2/RD1 OC4/RD3 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 dsPIC30F3011 40-Pin PDIP 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 AVDD AVSS PWM1L/RE0 PWM1H/RE1
dsPIC30F Pin Diagrams (Continued) 44 43 42 41 40 39 38 37 36 35 34 AN3/INDX/CN5/RB3 AN2/SS1/LVDIN/CN4/RB2 EMUC3/AN1/VREF-/CN3/RB1 EMUD3/AN0/VREF+/CN2/RB0 MCLR NC AVDD AVSS PWM1L/RE0 PWM1H/RE1 PWM2L/RE2 44-Pin TQFP dsPIC30F3011 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 PWM2H/RE3 PWM3L/RE4 PWM3H/RE5 VDD VSS NC RF0 RF1 U2RXRF4 U2TX/RF5 PGC/EMUC/U1RX/SDI1/SDA/RF2 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 FLTA/INT0/RE8 EMUD2/OC2/IC2/INT2/RD1 OC4/RD3 VSS NC VDD OC3/R
dsPIC30F Pin Diagrams (Continued) 44 43 42 41 40 39 38 37 36 35 34 AN3/INDX/CN5/RB3 AN2/SS1/LVDIN/CN4/RB2 EMUC3/AN1/VREF-/CN3/RB1 EMUD3/AN0/VREF+/CN2/RB0 MCLR NC AVDD AVSS PWM1L/RE0 PWM1H/RE1 PWM2L/RE2 44-Pin TQFP dsPIC30F4011 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 PWM2H/RE3 PWM3L/RE4 PWM3H/RE5 VDD VSS NC C1RX/RF0 C1TX/RF1 U2RXRF4 U2TX/RF5 PGC/EMUC/U1RX/SDI1/SDA/RF2 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 FLTA/INT0/RE8 EMUD2/OC2/IC2/INT2/RD1 OC4/RD3 VSS NC
dsPIC30F Pin Diagrams (Continued) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PWM3L/RE4 PWM2H/RE3 PWM2L/RE2 PWM1H/RE1 PWM1L/RE0 CTX1/RF1 CRX1/RF0 VDD VSS CN16/UPDN/RD7 CN15/RD6 CN14/RD5 CN13/RD4 OC4/RD3 OC3/RD2 EMUD2/OC2/RD1 64-pin TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dsPIC30F5015 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 EMUC1/SOSCO/T1CK/CN0/RC14 EMUD1/SOSCI/T4CK/CN1/RC13 EMUC2/OC1/RD0 INT4/RD11 INT3/RD10 IC2/FLTB/INT2/RD9 IC1/FLTA/INT1/RD8 VSS OSC2/CLKO/RC15 OSC1/CLKIN VDD SCL/RG2
dsPIC30F Pin Diagrams (Continued) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PWM3L/RE4 PWM2H/RE3 PWM2L/RE2 PWM1H/RE1 PWM1L/RE0 C1TX/RF1 C1RX/RF0 VDD VSS OC8/UPDN/CN16/RD7 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 EMUD2/OC2/RD1 64-pin TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dsPIC30F6015 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 EMUC1/SOSCO/T1CK/CN0/RC14 EMUD1/SOSCI/T4CK/CN1/RC13 EMUC2/OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/FLTB/INT2/RD9 IC1/FLTA/INT1/RD8 VSS OSC2/C
dsPIC30F Pin Diagrams (Continued) IC5/RD12 OC4/RD3 OC3/RD2 EMUD2/OC2/RD1 OC6/CN14/RD5 OC5/CN13/RD4 IC6/CN19/RD13 OC7/CN15/RD6 C2RX/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VDD VSS OC8/UPDN/CN16/RD7 PWM2L/RE2 PWM1H/RE1 PWM1L/RE0 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PWM3L/RE4 PWM2H/RE3 80-Pin TQFP PWM3H/RE5 1 PWM4L/RE6 2 60 EMUC1/SOSCO/T1CK/CN0/RC14 59 EMUD1/SOSCI/CN1/RC13 58 EMUC2/OC1/RD0 57 PWM4H/RE7 3 T2CK/RC1 T4CK/RC3 4 5 56 IC4/RD11 IC3/RD10 SCK2/CN8/RG6 6 55 IC2
dsPIC30F Pin Diagrams (Continued) IC5/RD12 OC4/RD3 OC3/RD2 EMUD2/OC2/RD1 OC6/CN14/RD5 OC5/CN13/RD4 IC6/CN19/RD13 OC7/CN15/RD6 C2RX/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VDD VSS OC8/CN16/UPDN/RD7 PWM2L/RE2 PWM1H/RE1 PWM1L/RE0 PWM2H/RE3 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PWM3L/RE4 80-Pin TQFP PWM3H/RE5 1 60 EMUC1/SOSCO/T1CK/CN0/RC14 PWM4L/RE6 2 59 EMUD1/SOSCI/CN1/RC13 PWM4H/RE7 3 58 EMUD2/OC1/RD0 T2CK/RC1 T4CK/RC3 SCK2/CN8/RG6 4 57 5 56 IC4/RD11 IC3/RD10 6 55 IC
dsPIC30F NOTES: © 2005 Microchip Technology Inc.
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