User's Manual
Table Of Contents
- Low-Power Long Range (LoRa®) Technology Gateway Module for US (LG9271) and EU (LG8271)
- 1.0 Device Overview
- 2.0 General Specifications
- TABLE 2-1: General Specification
- TABLE 2-2: Electrical Characteristics
- TABLE 2-3: RF Receiver Characteristics
- TABLE 2-4: LoRa Technology Data Rate (bps) and Sensitivity versus Spreading Factor (SF)
- TABLE 2-5: CURRENT CONSUMPTION (3.3V)
- TABLE 2-6: Module Dimensions
- TABLE 2-7: RF OUTPUT POWER (dBm) versus TX POWER SETTING (nominal)
- 3.0 Typical Hardware Connections
- 4.0 Application Information
- 5.0 Regulatory Approval
- Appendix A: Revision History
- Worldwide Sales and Service
2017 Microchip Technology Inc. Preliminary DS00000000A-page 7
LG8271/LG9271
2.0 GENERAL SPECIFICATIONS
Table 2-1 provide the general specifications for the module. Table 2-2 through Table 2-4 provide the electrical charac-
teristics, RF receiver charactersitics, LoRa Technology data rate and sensitivity versus spreading factor.
TABLE 2-1: GENERAL SPECIFICATION
Specification Description
Frequency Band - LG9271 902.000 MHz to 928.000 MHz
Frequency Band - LG8271 863.000 MHz to 870.000 MHz
Modulation Method FSK (EU only), GFSK (EU only), and LoRa
®
Technology
modulation
Maximum Over-the-Air Data Rate 200 kbps (FSK);
21875 bps (LoRa Technology, see Ta ble 2-4)
(1)
RF Connection On-board U.FL connector
Interface UART (TTL)
Operation Range Up to 15 km coverage at suburban; up to 5 km coverage at
urban area
RF TX Power - LG9271 Adjustable, < +18.5 dBm
(2)
RF TX Power - LG8271 Adjustable, < +14.0 dBm
(2)
Generated Conductive Harmonics Level Below -70 dBm
Temperature (operating) -40°C to +85°C
Temperature (storage) -40°C to +115°C
Humidity 10% ~ 90% Non-condensing
Note 1: Depends on modulation and Expand Spreading Factor (SF)
2: TX power is adjustable. For more information, refer to the “LoRa
®
Technology Gateway Module Software
Specifications”
TABLE 2-2: ELECTRICAL CHARACTERISTICS
Parameter Min. Typ. Max. Units
Supply Voltage 3.0 — 3.6 V
Voltage on any pin with respect to VSS (except
VDD)
-0.3 — -VDD + 0.3 V
Voltage on VDD with respect to VSS -0.3 — 3.9 V
Input Clamp Current (IIK) (VI < 0 or VI > VDD) — — +/-20 mA
Output Camp Current (IOK) (VO < 0 or VO >
VDD)
——+/-20mA
GPIO sink/source current each — — 25/25 mA
Total GPIO sink/source current — — 200/185 mA
RAM Data Retention Voltage (in Sleep mode or
Reset state)
1.5 — — V
VDD Start Voltage to ensure internal Power-on
Reset signal
——0.7V
VDD Rise Rate to ensure internal Power-on
Reset signal
0.05 — — V/ms
Brown-out Reset Voltage 1.75 1.9 2.05 V
Logic Input Low Voltage — — 0.15 x VDD V
Logic Input High Voltage 0.8 x VDD — - V
Input Leakage at <25°C (VSS<VPIN<VDD, Pin
at high-impedance)
— 0.1 50 nA