Datasheet

High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O
Datasheet
SMSC LAN9221/LAN9221i 127 Revision 2.9 (03-01-12)
DATASHEET
Chapter 6 Timing Diagrams
6.1 Equivalent Test Load
Output timing specifications assume an equivalent test load as illustrated in Figure 6.1 below.
6.2 Host Interface Timing
The LAN9221/LAN9221i supports the following host cycles:
Read Cycles:
 PIO Reads (nCS or nRD controlled)
 PIO Burst Reads (nCS or nRD controlled)
 RX Data FIFO Direct PIO Reads (nCS or nRD controlled)
 RX Data FIFO Direct PIO Burst Reads (nCS or nRD controlled)
Write Cycles:
 PIO writes (nCS and nWR controlled)
 TX Data FIFO direct PIO writes (nCS or nWR controlled)
All timing measurements were verified under the following conditions:
Note: The specified test load used for output timing is dependant on VDDVARIO.
Temperature: ................................................................................................................................ Note 6.1
Load Capacitance (VDDVARIO = 3.3V +/- 300mV):........................................................................ 25pF
Load Capacitance (VDDVARIO = 2.5V +/- 10%): ............................................................................ 10pF
Load Capacitance (VDDVARIO = 1.8V +/- 10%): ............................................................................ 10pF
Note 6.1 0
o
C to +70
o
C for commercial version, -40
o
C to +85
o
C for industrial version.
Figure 6.1 Equivalent Test Load
OUTPUT
Test load varies dependent on VDDVARIO:
VDDVARIO = 3.3V ± 300mV: 25pF
VDDVARIO = 2.5V ± 10%: 10pF
VDDVARIO=1.8V ± 10%: 10pF