Datasheet

High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O
Datasheet
SMSC LAN9221/LAN9221i 59 Revision 2.9 (03-01-12)
DATASHEET
3.12.6.3 TX Example 3
In this example a single, 111-Byte Ethernet packet will be transmitted with a TX checksum. This packet
is divided into four buffers. The four buffers are as follows:
Buffer 0:
 4-Byte “Data Start Offset”
 4-Byte Checksum Preamble
 16-Byte “Buffer End Alignment”
Buffer 1:
 7-Byte “Data Start Offset”
 79-Bytes of payload data
 16-Byte “Buffer End Alignment”
Buffer 2:
 0-Byte “Data Start Offset”
 15-Bytes of payload data
 16-Byte “Buffer End Alignment”
Buffer 3:
 10-Byte “Data Start Offset”
 17-Bytes of payload data
 16-Byte “Buffer End Alignment”
Figure 3.21, "TX Example 1" illustrates the TX command structure for this example, and also shows
how data is passed to the TX data FIFO.
Note: In order to perform a TX checksum calculation on the associated packet, bit 14 (CK) of the TX
Command ‘B’ must be set in conjunction with bit 13 (FS) of TX Command ‘A’ and bit 16
(TXCOE_EN) of the COE_CR register. For more information, refer to Section 3.6.2, "Transmit
Checksum Offload Engine (TXCOE)".