Datasheet

High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O
Datasheet
SMSC LAN9221/LAN9221i 11 Revision 2.9 (03-01-12)
DATASHEET
1.1 Block Diagram
The SMSC LAN9221/LAN9221i integrated 10/100 MAC/PHY controller is a peripheral chip that
performs the function of translating parallel data from a host controller into Ethernet packets. The
LAN9221/LAN9221i Ethernet MAC/PHY controller is designed and optimized to function in an
embedded environment. All communication is performed with programmed I/O transactions using the
simple SRAM-like host interface bus.
The diagram shown above, describes a typical system configuration of the LAN9221/LAN9221i in a
typical embedded environment.
The LAN9221/LAN9221i is a general purpose, platform independent, Ethernet controller. The
LAN9221/LAN9221i consists of four major functional blocks. The four blocks are:
 10/100 Ethernet PHY
 10/100 Ethernet MAC
 RX/TX FIFOs
 Host Bus Interface (HBI)
Figure 1.1 System Block Diagram
Microprocessor/
Microcontroller
LAN9221/
LAN9221i
Magnetics Ethernet
System
Peripherals
System Memory
EEPROM
(Optional)
LEDS/
GPIO
25MHz
XTAL
System Bus