Datasheet

High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O
Datasheet
SMSC LAN9221/LAN9221i 101 Revision 2.9 (03-01-12)
DATASHEET
0 Flow Control on Any Frame (FCANY). When this bit is set, the
LAN9221/LAN9221i will assert back pressure, or transmit a pause frame
when the AFC level is reached and any frame is received. Setting this bit
enables full-duplex flow control when the LAN9221/LAN9221i is operating in
full-duplex mode.
When this mode is enabled during half-duplex operation, the Flow Controller
does not decode the MAC address and will send a pause frame upon
receipt of a valid preamble (i.e., immediately at the beginning of the next
frame after the RX data FIFO level is reached).
When this mode is enabled during full-duplex operation, the Flow Controller
will immediately instruct the MAC to send a pause frame when the RX data
FIFO level is reached. The MAC will queue the pause frame transmission
for the next available window.
Setting this bit overrides bits [3:1] of this register.
R/W 0
Table 5.5 Backpressure Duration Bit Mapping
BACKPRESSURE DURATION
[19:16] 100Mbs Mode 10Mbs Mode
0h 5uS 7.2uS
1h 10uS 12.2uS
2h 15uS 17.2uS
3h 25uS 27.2uS
4h 50uS 52.2uS
5h 100uS 102.2uS
6h 150uS 152.2uS
7h 200uS 202.2uS
8h 250uS 252.2uS
9h 300uS 302.2uS
Ah 350uS 352.2uS
Bh 400uS 402.2uS
Ch 450uS 452.2uS
Dh 500uS 502.2uS
Eh 550uS 552.2uS
Fh 600uS 602.2uS
BITS DESCRIPTION TYPE DEFAULT