Datasheet

16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support
Datasheet
SMSC LAN9220 83 Revision 2.9 (03-01-12)
DATASHEET
12:11 Reserved RO -
10 TX Data FIFO Overrun Interrupt (TDFO). Generated when the TX data
FIFO is full, and another write is attempted.
R/WC 0
9 TX Data FIFO Available Interrupt (TDFA). Generated when the TX data
FIFO available space is greater than the programmed level.
R/WC 0
8 TX Status FIFO Full Interrupt (TSFF). Generated when the TX Status
FIFO is full.
R/WC 0
7 TX Status FIFO Level Interrupt (TSFL). Generated when the TX Status
FIFO reaches the programmed level.
R/WC 0
6 RX Dropped Frame Interrupt (RXDF_INT). This interrupt is issued
whenever a receive frame is dropped.
R/WC 0
5 Reserved RO -
4 RX Status FIFO Full Interrupt (RSFF). Generated when the RX Status
FIFO is full.
R/WC 0
3 RX Status FIFO Level Interrupt (RSFL). Generated when the RX Status
FIFO reaches the programmed level.
R/WC 0
2-0 GPIO [2:0] (GPIOx_INT). Interrupts are generated from the GPIO’s.
These interrupts are configured through the GPIO_CFG register.
R/WC 000
BITS DESCRIPTION TYPE DEFAULT