Datasheet

16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support
Datasheet
SMSC LAN9220 35 Revision 2.9 (03-01-12)
DATASHEET
Data path operations for the various supported endianess and word swap configurations are illustrated
in Figure 3.9. Table 3.8, "Endian Ordering Logic Operation" illustrates the byte ordering applied by the
endian logic for each type of host access. This figure and table assume an internal byte ordering of 3-
2-1-0, where ‘3’ is the most significant byte (data[31:24]) and ‘0’ is the least significant byte (data[7:0]).
Figure 3.8 LAN9220 Host Data Path Diagram
"WORD SWAP"
Logic
FIFO Port Endian Ordering
Logic
RX/TX Data FIFO Port
Access (addresses 00h to
3Ch)
Direct FIFO Access Endian
Ordering Logic
RX/TX Data FIFO Direct
Access
(FIFO_SEL = 1)
CSRs and Status FIFOs
FPORTEND
(HW_CFG[29])
FSELEND
(HW_CFG[28])
D[15:0]
(Host Data Bus)
WORD_SWAP