Datasheet

16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support
Datasheet
SMSC LAN9220 131 Revision 2.9 (03-01-12)
DATASHEET
Note: A PIO Read cycle begins when both nCS and nRD are asserted. The cycle ends when either
or both nCS and nRD are deasserted. They may be asserted and deasserted in any order.
Parameters t
csh
and t
csl
must be extended using wait states to meet the t
cycle
minimum.
6.4 PIO Burst Reads
In this mode, performance is improved by allowing up to 16 WORD read cycles back-to-back. PIO
Burst Reads can be performed using Chip Select (nCS) or Read Enable (nRD). Either or both of these
control signals must go high between bursts for the period specified.
Note: The “Data Bus” width is 16 bits
Note 6.3 When VDDVARIO is 3.3V or 2.5V, the maximum T
doff
time is 7ns. When VDDVARIO is
1.8V, the maximum T
doff
time is 9ns.
Note: A PIO Burst Read cycle begins when both nCS and nRD are asserted. The cycle ends when
either or both nCS and nRD are deasserted. They may be asserted and deasserted in any
order.
Figure 6.3 PIO Burst Read Cycle Timing
Table 6.4 PIO Burst Read Timing
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
csh
nCS, nRD Deassertion Time 13 ns
t
csdv
nCS, nRD Valid to Data Valid 30 ns
t
acyc
Address Cycle Time 165
t
asu
Address Setup to nCS, nRD valid 0 ns
t
adv
Address Stable to Data Valid 40
t
ah
Address Hold Time 0 ns
t
don
Data Buffer Turn On Time 0 ns
t
doff
Data Buffer Turn Off Time Note 6.3 ns
t
doh
Data Output Hold Time 0 ns
Data Bus
nCS, nRD
A[
7:5
]
A[
4:1
]