Datasheet

16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support
Datasheet
Revision 2.9 (03-01-12) 130 SMSC LAN9220
DATASHEET
6.3 PIO Reads
PIO reads can be used to access CSRs or RX Data and RX/TX status FIFOs. In this mode, counters
in the CSRs are latched at the beginning of the read cycle. Read data is valid as indicated in the timing
diagram. PIO reads can be performed using Chip Select (nCS) or Read Enable (nRD). Either or both
of these control signals must go high between cycles for the period specified.
Note: Some registers have restrictions on the timing of back-to-back, write-read and read-read
cycles.
Note: The “Data Bus” width is 16 bits
Note 6.2 When VDDVARIO is 3.3V or 2.5V, the maximum T
doff
time is 7ns. When VDDVARIO is
1.8V, the maximum T
doff
time is 9ns.
Figure 6.2 PIO Read Cycle Timing
Table 6.3 PIO Read Timing
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
cycle
Read Cycle Time 165 ns
t
csl
nCS, nRD Assertion Time 32 ns
t
csh
nCS, nRD Deassertion Time (see Note below) 13 133 ns
t
csdv
nCS, nRD Valid to Data Valid 30 ns
t
asu
Address Setup to nCS, nRD Valid 0 ns
t
ah
Address Hold Time 0 ns
t
don
Data Buffer Turn On Time 0 ns
t
doff
Data Buffer Turn Off Time Note 6.2 ns
t
doh
Data Output Hold Time 0 ns
Data Bus
nCS, nRD
A[
7:1
]