Datasheet

16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support
Datasheet
Revision 2.9 (03-01-12) 116 SMSC LAN9220
DATASHEET
5.4.13 COE_CR—Checksum Offload Engine Control Register
This register controls the transmit and receive checksum offload engines.
Offset: D Attribute: R/W
Default Value: 00000000h Size: 32 bits
BITS DESCRIPTION
31-17 Reserved
16 TX Checksum Offload Engine Enable (TXCOE_EN). This bit enables/disables the Transmit COE.
This bit may only be changed if the TX data path is disabled.
0: The TXCOE is bypassed
1: The TXCOE is enabled
15-2 Reserved
1 RX Checksum Offload Engine Mode (RXCOE_MODE) This register indicates whether the RXCOE
will check for VLAN tags or a SNAP header prior to beginning its checksum calculation. In its default
mode, the calculation will always begin 14 bytes into the frame.
The RXCOE_MODE may only be changed if the ESS RX path is disabled.
0: Begin checksum calculation after first 14 bytes of Ethernet Frame
1: Begin checksum calculation at start of L3 packet by adjusting for VLAN tags and/or SNAP header.
0 RX Checksum Offload Engine Enable (RXCOE_EN). This bit enables/disables the Receive COE.
This bit may only be changed if the RX data path is disabled.
0: The RXCOE is bypassed
1: The RXCOE is enabled
Note: When the RXCOE is enabled, automatic pad stripping must be disabled (bit 8 (PADSTR) of
the MAC_CR—MAC Control Register) and vice versa. These functions cannot be enabled
simultaneously.