Datasheet

Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
Datasheet
Revision 1.0 (10-24-08) Page 84 SMSC LAN91C96 5v&3v
DATASHEET
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CPU ADDRESS
CSMA ADDRESS
RX PACKET
NUMBER
RX FIFO
PAC K E T N UMBE R
PACKET NUMBER
REGISTER
PACK # OUT
TX DONE
PACKET NUMBER
ALLOCATION
RESULT REGISTE
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ALLOCATE
RELEASE
PACK # OUT
DMA
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TX
DECODER
MMU
COMMAND
REGISTER
ALLOCATE RELEASE
INT
FIGURE 9.1 - MMU PACKET NUMBER FLOW AND RELEVANT REGISTERS
9.8 CSMA Block
The CSMA/CD block is first interfaced via its control registers in order to define its operational
configuration. From then on, the DMA interface between the CSMA/CD block and memory is used to
transfer data to and from its data path interface.
For transmit, the CSMA/CD block will be asked to transmit frames as soon as they are ready in memory. It
will continue transmissions until any of the following transmit error occurs:
1. Collisions on same frame
2. Late collision
3. Lost Carrier sense and MON_CSN set
4. SQET error and STP_SQET set
In that case TXENA will be cleared and the CPU should restart the transmission by setting it again. If a
transmission is successful, TXENA stays set and the CSMA/CD is provided by the DMA block with the
next packet to be transmitted.