Datasheet

Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
Datasheet
Revision 1.0 (10-24-08) Page 60 SMSC LAN91C96 5v&3v
DATASHEET
TX EMPTY INT - Set if the TX FIFO goes empty, can be used to generate a single interrupt at the end of a
sequence of packets enqueued for transmission. This bit latches the empty condition, and the bit will stay
set until it is specifically cleared by writing the acknowledge register with the TX EMPTY INT bit set. If a
real time reading of the FIFO empty is desired, the bit should be first cleared and then read.
The TX_EMPTY MASK bit should only be set after the following steps:
a) A packet is enqueued for transmission
b) The previous empty condition is cleared (acknowledged)
TX INT - Set when at least one packet transmission was completed or any of the below transmit fatal
errors occurs:
1. SQET - SQE Error
2. LOST CARR - Lost Carrier
3. LATCOL - Late Collision
4. 16COL - 16 collisions
The first packet number to be serviced can be read from the FIFO PORTS register. The TX INT bit is
always the logic complement of the TEMPTY bit in the FIFO PORTS register. After servicing a packet
number, its TX INT interrupt is removed by writing the Interrupt Acknowledge Register with the TX INT bit
set.
RCV INT - Set when a receive interrupt is generated. The first packet number to be serviced can be read
from the FIFO PORTS register. The RCV INT bit is always the logic complement of the REMPTY bit in the
FIFO PORTS register.
Receive Interrupt is cleared when RX FIFO is empty.
Notes:
 For edge triggered systems, the Interrupt Service Routine should clear the Interrupt Mask Register, and only
enable the appropriate interrupts after the interrupt source is serviced (acknowledged).