Datasheet
Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
Datasheet
Revision 1.0 (10-24-08) Page 58 SMSC LAN91C96 5v&3v
DATASHEET
This register is mapped into two uni-directional FIFOs that allow moving words to and from the LAN91C96
regardless of whether the pointer address is even or odd. Data goes through the write FIFO into memory,
and is pre-fetched from memory into the read FIFO. If byte accesses are used, the appropriate (next) byte
can be accessed through the Data Low or Data High registers. The order to and from the FIFO is
preserved. Byte and word accesses can be mixed on the fly in any order.
This register is mapped into two consecutive word locations to facilitate the usage of double word move
instructions. The DATA register is accessible at any address in the 8 through Ah range, while the number
of bytes being transferred are determined by A0 and nSBHE in LOCAL BUS mode, and by A0, nCE1 and
nCE2 in PCMCIA mode.
I/O SPACE - BANK2
OFFSET NAME TYPE SYMBOL
C INTERRUPT STATUS REGISTER READ ONLY IST
TX IDLE
INT
Reserved
EPH
INT
RX_
OVRN
INT
ALLOC
INT
TX
EMPTY
INT
TX INT
RCV INT
0 0 0 0 0 1 0 0
OFFSET NAME TYPE SYMBOL
C INTERRUPT ACKNOWLEDGE REGISTER WRITE ONLY ACK
Reserved
RX_
OVRN
INT
TX
EMPTY
INT
TX INT
OFFSET NAME TYPE SYMBOL
D INTERRUPT MASK REGISTER READ/WRITE MSK
TX IDLE
INT
MASK
Reserved
EPH
INT
MASK
RX_
OVRN
INT
MASK
ALLOC
INT
MASK
TX
EMPTY
INT
MASK
TX INT
MASK
RCV INT
MASK
0 0 0 0 0 0 0 0
This register can be read and written as a word or as two individual bytes.
The Interrupt Mask Register bits enable the appropriate bits when high and disable them when low. A
MASK bit being set will cause a hardware interrupt.
TX IDLE INT - Transmit Idle interrupt. Set when the transmit state machine is not active. This bit is used
under the condition where the TX FIFO is still NOT empty, the transmitter is disabled and the host wants to
determine when the transmitter is completed with the current transmit packet. This event usually happens
when the host wants to insert at the head of the transmit queue a frame for example.
Typical flow of events/Condition:
1. The transmit FIFO is not empty
2. The transmit DONE FIFO is either empty or not empty
3. The transmit engine is either active or not active