Datasheet

Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet

Datasheet

Revision 1.0 (10-24-08) Page 52 SMSC LAN91C96 5v&3v

DATASHEET

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OFFSET NAME TYPE SYMBOL

A GENERAL ADDRESS REGISTERS READ/WRITE GPR

HIGH DATA BYTE

0 0 0 0 0 0 0 0

LOW DATA BYTE

0 0 0 0 0 0 0 0

This register can be used as a way of storing and retrieving non-volatile information in the EEPROM to be

used by the software driver. The storage is word oriented, and the EEPROM word address to be read or

written is specified using the six lowest bits of the Pointer Register.

This register can also be used to sequentially program the Individual Address area of the EEPROM, that is

normally protected from accidental Store operations.

This register will be used for EEPROM read and write only when the EEPROM SELECT bit in the Control

the LAN91C96.

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OFFSET NAME TYPE SYMBOL

C CONTROL REGISTER READ/WRITE CTR

0 RCV_

BAD

PWRDN

WAKEUP

_EN

AUTO

RELEAS

0 0 0 0 0 X X 1

ENABLE

EEPROM

SELECT

RELOAD STORE

0 0 0 X X 0 0 0

RCV_BAD - When set, bad CRC packets are received. When clear bad CRC packets do not generate

interrupts and their memory is released.

PWRDN - Active high bit used to put the Ethernet function in power down mode.

Cleared by:

1. A write to any register in the LAN91C96 I/O space.

2. Hardware reset. This bit is combined with the Pwrdwn bit in ECSR and with the powerdown bit to

determine when the function is powered down.

WAKUP_EN - Active high bit used to enable the controller in the appropriate power down modes to power

up and set the WAKEUP bit in the EPHSR -> generate an EPH interrupt(if not masked). When clear (0),

no “Magic Packet” scanning is done on receive packets.

Note

: Setting (1) the bit is meaningful only if the function is enabled (Enable Function bit in COR; offset 8000h).