Datasheet

Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
Datasheet
Revision 1.0 (10-24-08) Page 50 SMSC LAN91C96 5v&3v
DATASHEET
INT SEL1-0 - In LOCAL BUS mode, used to select one out of four interrupt pins. The three
unused interrupts are tristated.
INT SEL1 INT SEL0 INTERRUPT PIN USED
0 0 INTR0
0 1 INTR1
1 0 INTR2
1 1 INTR3
I/O SPACE - BANK1
OFFSET NAME TYPE SYMBOL
2 BASE ADDRESS REGISTER READ/WRITE BAR
For LOCAL BUS mode only, this register holds the I/O address decode option chosen for the I/O and ROM
space. It is part of the EEPROM saved setup, and is not usually modified during run-time.
A15 A14 A13 A9 A8 A7 A6 A5
0 0 0 1 1 0 0 0
ROM SIZE RA18 RA17 RA16 RA15 RA14
0 1 1 0 0 1 1 1
A15 - A13 and A9 - A5 - These bits are compared in LOCAL BUS mode against the I/O address on the
bus to determine the IOBASE for LAN91C96 registers. The 64k I/O space is fully decoded by the
LAN91C96 down to a 16 location space, therefore the unspecified address lines A4, A10, A11 and A12
must be all zeros.
ROM SIZE - Determines the ROM decode area in LOCAL BUS mode memory space as follows:
00 = ROM disable
01 = 16k: RA14-18 define ROM select.
10 = 32k: RA15-18 define ROM select.
11 = 64k: RA16-18 define ROM select.
RA18-RA14 - These bits are compared in LOCAL BUS mode against the memory address on the bus to
determine if the ROM is being accessed, as a function of the ROM SIZE. ROM accesses are read only
memory accesses defined by MEMRD* going low.
For a full decode of the address space unspecified upper address lines have to be: A19 = "1", A20-A23
lines are not directly decoded, however LOCAL BUS systems will only activate SMEMRD* only when A20-
A23=0.
All bits in this register are loaded from the serial EEPROM in LOCAL BUS Mode only. In PCMCIA mode,
the I/O base is set to the default value (as in LOCAL BUS mode) as defined below.
The I/O base decode defaults to 300h (namely, the high byte defaults to 18h). ROM SIZE defaults to 01.
ROM decode defaults to CC000 (namely the low byte defaults to 67h).
Below chart shows the decoding of I/O Base Address 300h:
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0