Datasheet

Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
Datasheet
Revision 1.0 (10-24-08) Page 48 SMSC LAN91C96 5v&3v
DATASHEET
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OFFSET NAME TYPE SYMBOL
8 MEMORY INFORMATION REGISTER READ ONLY MIR
For software compatibility with other LAN9000 parts all memory-related information is represented in 256 x
M byte units, where the multiplier M is determined by the MCR upper byte. M equals “1” for the
LAN91C96.
FREE MEMORY AVAILABLE (in BYTES* 256* M)
0 0 0 1 1 0 0 0
MEMORY SIZE (in BYTES* 256* M)
0 0 0 1 1 0 0 0
FREE MEMORY AVAILABLE - This register can be read at any time to determine the amount of free
memory. The register defaults to the MEMORY SIZE upon reset or upon the RESET MMU command.
MEMORY SIZE - This register can be read to determine the total memory size, and will always read 18H
(6144 bytes) for the LAN91C96.
MEMORY SIZE REGISTER M ACTUAL MEMORY
LAN91C90 FFH 1 64 kbytes
LAN91C90 40H 1 16 kbytes
LAN91C92/
LAN91C94
12H 1 4608 bytes
LAN91C95 18H 1 6144 bytes
LAN91C96 18H 1 6144 bytes
LAN91C100 FFH 2 128 kbytes
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OFFSET NAME TYPE SYMBOL
A
MEMORY CONFIGURATION
REGISTER
LOWER BYTE READ/WRITE
UPPER BYTE READ ONLY
MCR
Memory Size Multiplier “M”
0 0 1 1 0 0 1 1
Memory Reserved for Transmit (in BYTES * 256 * M)
0 0 0 0 0 0 0 0
MEMORY RESERVED FOR TRANSMIT
Programming this value allows the host CPU to reserve memory to be used later for transmit, limiting the
amount of memory that receive packets can use up. When programmed for zero, the memory allocation
between transmit and receive is completely dynamic. When programmed for a non-zero value, the
allocation is dynamic if the free memory exceeds the programmed value, while receive allocation requests
are denied if the free memory is less or equal to the programmed value. This register defaults to zero
upon reset. It is not affected by the RESET MMU command.
The value written to the MCR is a reserved memory space IN ADDITION TO ANY MEMORY
CURRENTLY IN USE. If the memory allocated for transmit plus the reserved space for transmit is required
to be constant (rather than grow with transmit allocations) the CPU should update the value of this register
after allocating or releasing memory.
The contents of MIR as well as the low byte of MCR are specified in 256* M bytes. The multiplier M is
determined by bits 11, 10 and 9 as follows: