Datasheet

Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
Datasheet
Revision 1.0 (10-24-08) Page 32 SMSC LAN91C96 5v&3v
DATASHEET
Table 5.5 - Interrupt Merging
FUNCTION PCMCIA MODE LOCAL BUS MODE
Interrupt Output
nIREQ when function is Ready.
Acts as ready line at power up.
I.e. remains low until the chip
(therefore, card) is Ready
INTR0-3
Ethernet Interrupt Source
OR function of all interrupt bits specified in the Interrupt Status Register
ANDed with their respective Enable bits
Ethernet Interrupt Enable
Not Applicable in LOCAL BUS
mode
Ethernet Interrupt Status Bit Intr bit in ECSR
5.3 Reset Logic
The pins and bits involved in the different reset mechanisms are:
RESET - Input Pin
SRESET - Soft Reset bit in ECOR, or the SRESET bit
SOFT RST - EPH Soft Reset bit in RCR
RESETS THE FOLLOWING
FUNCTIONS
SAMPLES
LOCAL BUS
VS. PCMCIA
MODE
TRIGGERS
EEPROM
READ
RESET pin All internal logic Yes Yes
ECOR
Register
SRESET bit
The Ethernet controller function and
Ethernet PCMCIA Configuration Registers
except for the bit itself. Setting this bit also
lowers the nIREQ/READY line. When
cleared, the nIREQ/READY line is raised.
No Yes
SOFT RST
The Ethernet controller itself except for
the IA, CONF and BASE registers. It does
not reset any PCMCIA Configuration
Register.
No No
5.4 Power Down Logic States
Table 5.6, Table 5.7, Table 5.8, and Table 5.9 describe the power down states of the LAN91C96. The
pins and bits involved in power down are:
1. PWRDWN/TXCLK - Input pin valid when XENDEC is not zero (0).
2. Pwrdwn bits in ECSR
3. Enable Function bit in ECOR
4. PWRDN - Legacy power down bit in Control Register.