Datasheet

Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
Datasheet
SMSC LAN91C96 5v&3v Page 31 Revision 1.0 (10-24-08)
DATASHEET
Table 5.3 - Bus Transactions In PCMCIA Mode
A0 NCE1 NCE2 D0-7 D8-15
8 BIT MODE
((IOis8=1) +
(nEN16=1).
(16BIT=0))
0 0 X Even byte -
1 0 X Odd byte -
X 1 X NO CYCLE
16 BIT MODE
otherwise
0 0 0 Even byte Odd byte
0 0 1 Even byte -
1 0 1 Odd byte
X 1 0 - Odd byte
X 1 1 NO CYCLE
Table 5.4 - Bus Transactions In 68000 Mode
D0-7 D8-15
8 BIT MODE ILLEGAL ACCESS
16 BIT MODE
(A0=0).(nSBHE=0)
Even byte Odd byte
16BIT: CONFIGURATION REGISTER bit 7
IOis8: CSR register bit 5
nEN16: pin nEN16
8 Bit mode: ((IOis8 = 1) + (nMIS16 = 1)
5.2 Interrupt Structure
The Ethernet interrupt is conceptually equivalent to the LAN91C94 interrupt line, it is the or function of all
enabled interrupts within the Ethernet core. The enabling, reporting, and clearing of these sources is
controlled by the ECOR register. The interrupt structure is similar for LOCAL BUS and PCMCIA modes
with the following exceptions:
PCMCIA uses a single interrupt pin (nIREQ) while LOCAL BUS can use any of four INTR0-3 pins.