Datasheet

Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
Datasheet
SMSC LAN91C96 5v&3v Page 3 Revision 1.0 (10-24-08)
DATASHEET
Table of Contents
CHAPTER 1 GENERAL DESCRIPTION ..................................................................... 7
CHAPTER 2 OVERVIEW............................................................................................. 8
CHAPTER 3 PIN CONFIGURATIONS....................................................................... 11
3.1 Local Bus vs. PCMCIA vs. 68000 Pin Requirements...................................................................................15
CHAPTER 4 DESCRIPTION OF PIN FUNCTIONS ................................................... 17
4.1 Buffer Symbols................................................................................................................................................21
CHAPTER 5 FUNCTIONAL DESCRIPTION.............................................................. 23
5.1 Buffer Memory................................................................................................................................................24
5.2 Interrupt Structure.........................................................................................................................................31
5.3 Reset Logic.......................................................................................................................................................32
5.4 Power Down Logic States...............................................................................................................................32
5.5 LAN91C96 Power Down States.....................................................................................................................33
5.6 PCMCIA CONFIGURATION REGISTERS DESCRIPTION..................................................................36
CHAPTER 6 FRAME FORMAT IN BUFFER MEMORY FOR ETHERNET ...............38
CHAPTER 7 REGISTERS MAP IN I/O SPACE......................................................... 42
7.1 I/O Space Access .............................................................................................................................................42
7.2 I/O Space Registers Description ....................................................................................................................42
CHAPTER 8 THEORY OF OPERATION ................................................................... 65
8.1 Typical Flow of Events for Transmit (Auto Release = 0) ............................................................................67
8.2 Typical Flow of Events for Transmit (Auto Release = 1) ............................................................................68
8.3 Flow of Events for Receive.............................................................................................................................69
CHAPTER 9 FUNCTIONAL DESCRIPTION OF THE BLOCKS................................79