Datasheet

Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
Datasheet
Revision 1.0 (10-24-08) Page 122 SMSC LAN91C96 5v&3v
DATASHEET
CLOCK
t2
t2
t1
tR
tF
Figure 12.26 – Input Clock Timing
NAME DESCRIPTION MIN TYP MAX UNITS
t1 Clock Cycle Time for 20 MHz 50 ns
t2 Clock High Time/Low Time for 20 MHz 30/20 20/30 ns
tR, tF Clock Rise Time/Fall Time 5 ns
Xtal1 Startup time (from 1.6v of Vcc rising) 50 msec
Xtal1 Capture Range (Xtal1 frequency
variation)
19.7 20.3 MHz
Xtal Internal feedback resistor 1 3 Meg Ohm
ADDRESS
DATA
REGISTER
POINTER
REGISTER
nIOWR
t45
t45 Last Access to Data Register to Pointer
Reloaded
Parameter min typ max units
ns2 * t20
Figure 12.27 – Memory Write Timing