Datasheet

Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
Datasheet
Revision 1.0 (10-24-08) Page 104 SMSC LAN91C96 5v&3v
DATASHEET
Figure 12.6 – Local Bus Consecutive Read and Write Cycles
t20
A0-15
AEN,
nSBHE
nIOCS16
nIOWR
D0-D15
VALID ADDRESS
VALID ADDRESS
nIORD
t9
t10
ZZ Z
VALID DATA
VALID DATA
IOCHRDY
Z
Z
Control Active to IOCHRDY Low
IOCHRDY Low Pulse Width*
Cycle time**
Parameter min typ max units
100
185
12
150
ns
ns
ns
t9
t10
t20
*Note: Assuming NO WAIT ST = 0 in configuration register and cycle time observed.
**Note: The cycle time is defined only for accesses to the Data Register as follows:
For Data Register Read - From nIORD falling to next nIORD falling
For Data Register Write - From nIOWR rising to next nIOWR rising