Datasheet

Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
Datasheet
SMSC LAN91C96 5v&3v Page 101 Revision 1.0 (10-24-08)
DATASHEET
Figure 12.3 - PCMCIA Consecutive Read Cycles
ns
ns
ns
ns
ns
ns
ns
ns
ns
35
40
0
5
5
185
0
15
25
15
0
Parameter
t46
t47
t48
t20
t49
t50
t51
t52
t53
nIORD to INPACK Delay
nREG Low to Control Active
nCE1,nCE2 Setup to Control Active
Cycle Time (No Wait States)
nREG Hold after Control Active
nCE1,nCE2 Hold after Control Inactive
Address Setup to Control Active
Address Hold after Control Inactive
nIORD Active to Data Valid
min typ max units
t51 t52
t47
t49
t48
t50
t20
t53
t46 t46
valid
valid
A0-9,A15
nREG
nCE1,nCE2
nIORD
D0-15
nINPACK