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SMSC LAN91C96 5v&3v Revision 1.0 (10-24-08)

DATASHEET

LAN91C96

Non-PCI Single-Chip

Full Duplex Ethernet

Controller with Magic

Packet

Datasheet

Product Features

 Non-PCI Single-Chip Ethernet Controller

 A Subset of Motorola 68000 Bus Interface

Support

 Fully Supports Full Duplex Switched Ethernet

 Supports Enhanced Transmit Queue

Management

 6K Bytes of On-Chip RAM

 Supports IEEE 802.3 (ANSI 8802-3) Ethernet

Standards

 Automatic Detection of TX/RX Polarity Reversal

 Enhanced Power Management Features

 Supports “Magic Packet” Power Management

Technology

 Hardware Memory Management Unit

 Optional Configuration via Serial EEPROM

Interface (Jumperless)

 Supports single +5V or +3.3V (for Revisions E

and Later) VCC Designs

 Supports Mixed Voltage External PHY Designs

 Low Power CMOS Design

 100 Pin QFP and TQFP (1.0 mm body

Thickness) Lead-Free RoHS Compliant

Packages

 Pin Compatible with the LAN91C92 and

LAN91C94

Bus Interface

 Direct Interface to Local Bus, PCMCIA, and

68000 Buses with No Wait States

 Flexible Bus Interface

 16 Bit Data and Control Paths

 Fast Access Time

 Pipelined Data Path

 Handles Block Word Transfers for any

Alignment

Refer to Description of Pin Functions on Page 17 for

5V tolerant pins

 High Performance Chained ("Back-to-Back")

Transmit and Receive

 Pin Compatible with the LAN91C92 (in Local

Bus Mode) and the LAN91C94 in Both Local

Bus and PCMCIA Modes

 Dynamic Memory Allocation Between Transmit

and Receive

 Flat Memory Structure for Low CPU Overhead

 Buffered Architecture, Insensitive to Bus

Latencies (No Overruns/Underruns)

 Supports Boot PROM for Diskless Local Bus

Applications

Network Interface

 Integrated 10BASE-T Transceiver Functions:

- Driver and Receiver

- Link Integrity Test

- Receive Polarity Detection and Correction

 Integrated AUI Interface

 10 Mb/s Manchester Encoding/Decoding and

Clock Recovery

 Automatic Retransmission, Bad Packet

Rejection, and Transmit Padding

 External and Internal Loopback Modes

 Four Direct Driven LEDs for Status/ Diagnostics

Software Drivers

 LAN9000 Drivers for Major Network Operating

Systems Utilizing Local Bus or PCMCIA

Interface

 Software Drivers Compatible with the

LAN91C92, LAN91C94, LAN91C100FD (100

Mb/s), and LAN91C110 (100 Mb/s) Controllers

in Local Bus Mode

 Software Drivers Utilize Full Capability of 32 Bit

Microprocessor

Summary of content (125 pages)

PAGE 1
LAN91C96 Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet Product Features Non-PCI Single-Chip Ethernet Controller A Subset of Motorola 68000 Bus Interface Support High Performance Chained ("Back-to-Back") Transmit and Receive Fully Supports Full Duplex Switched Ethernet Supports Enhanced Transmit Queue Management Pin Compatible with the LAN91C92 (in Local Bus Mode) and the LAN91C94 in Both Local Bus and PCMCIA Modes 6K Bytes of On-Chip RAM Dyna
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet ORDER NUMBERS: LAN91C96-MS for 100 pin, QFP Lead-Free RoHS Compliant package LAN91C96-MU for 100 pin, TQFP Lead-Free RoHS Compliant package 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © 2008 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet Table of Contents CHAPTER 1 GENERAL DESCRIPTION ..................................................................... 7 CHAPTER 2 OVERVIEW ............................................................................................. 8 CHAPTER 3 PIN CONFIGURATIONS....................................................................... 11 3.1 Local Bus vs. PCMCIA vs. 68000 Pin Requirements.........................................
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet 9.1 Memory Management Unit ............................................................................................................................79 9.2 Arbiter .............................................................................................................................................................79 9.3 Bus Interface ..................................................................................
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet CHAPTER 12 TIMING DIAGRAMS ........................................................................... 99 CHAPTER 13 LAN91C96 REVISIONS .................................................................... 125 List of Figures Figure 3.1 - LAN91C96 100 Pin QFP...........................................................................................................................11 Figure 3.2 - LAN91C96 100 Pin TQFP.........
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet List of Tables Table 5.1 - LAN91C96 Address Space ........................................................................................................................30 Table 5.2 - Bus Transactions In LOCAL BUS Mode ....................................................................................................30 Table 5.3 - Bus Transactions In PCMCIA Mode.................................................................
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet Chapter 1 General Description The LAN91C96 is a VLSI Ethernet Controller that combines Local Bus, PCMCIA, and Motorola 68000 bus interfaces in one chip. LAN91C96 integrates all MAC and physical layer functions, as well as the packet RAM, needed to implement a high performance 10BASE-T (twisted pair) node.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet Chapter 2 Overview A unique architecture allows the LAN91C96 to combine high performance, flexibility, high integration and simple software interface. The LAN91C96 incorporates the LAN91C92 functionality for LOCAL BUS environments, as well as a PCMCIA interface and attribute registers like the LAN91C94 It also includes a subset of the Motorola 68000 interface.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet PCMCIA interface 68000 interface EEPROM interface Encoder/decoder with AUI interface 10BASE-T transceiver High performance: Chained ("Back-to-back") packet handling with no CPU intervention: Queues transmit packets Queues receive packets Stores results in memory along with packet Queues interrupts Optional single interrupt upon completion of transmit chain Fast block move operation for lo
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet Motorola 68000: Note: Uses non-volatile jumperless setup via serial EEPROM. The device must power up in LOCAL BUS mode with nIORD and nIOWR asserted simultaneously to make the controller enter the 68000 mode. The first write to the 68000 configured controller must be a write. Revision 1.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet Chapter 3 Pin Configurations nIORD/xDS nIOWR/R/nW nMEMR/nOE AEN/nREG/nAS IOCHRDY/nWAIT VSS D0 D1 D2 D3 VDD D4 D5 D6 D7 VSS RESET PWRDWN/TXCLK BSELED/RXD nLNKLED/TXD nRXLED/RXCLK nTXLED/nTXEN AVDD TPETXDP TPETXN TPETXDN TPETXP TXN/nCRS TXP/nCOLL AVSS AVDD COLN COLP RECN RECP TPERXN TPERXP AVSS AVSS RBIAS AVDD nXENDEC nEN16 VSS nROM/nPCMCIA XTAL1 XTAL2 IOS0 IOS1 VDD 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 6
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 TXN/nCRS TXP/nCOLL AVSS AVDD COLN COLP RECN RECP TPERXN TPERXP AVSS AVSS RBIAS AVDD nXENDEC nEN16 VSS nROM/nPCMCIA XTAL1 XTAL2 IOS0 IOS1 VDD IOS2 VSS ENEEP EEDO/SDOUT EEDI EECS EESK VSS D8 D9 D10 D11 VDD D12 D13 D14 D15 VSS INTR0/nIREQ/INTR INTR1/nINPACK VDD INTR2 INTR3 VSS nIOCS16/nI
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet PCMCIA CONNECTOR nCE1, nCE2, nREG, nWE A0-9, A15 10BASE-T / AUI INTERFACE nIORD, nIOWR STSCHG RESET nIREQ D0-15 LAN91C96 nIOIS16, nINPACK nWAIT nOE nFWE nFCS nWE nCE CS,SK,DI,DO nOE Extended D0-7 Attribute Eprom A0-X 2816 (PCMCIA) Serial Eprom (ISA-Hy9346) SINGLE FUNCTION PCMCIA CARD WITH THE LAN91C96 Figure 3.3 - LAN91C96 System Block Diagram SMSC LAN91C96 5v&3v Page 13 DATASHEET Revision 1.
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Revision 1.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet 3.1 Local Bus vs. PCMCIA vs. 68000 Pin Requirements FUNCTION SYSTEM ADDRESS BUS SYSTEM DATA BUS SYSTEM CONTROL BUS SERIAL EEPROM CRYSTAL OSC.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet FUNCTION LEDs MISC. Revision 1.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet Chapter 4 Description of Pin Functions PIN NO. TQFP QFP 93 95 26-28 30-36 37 28,29, 30, 3238 39 39 41 40-46 42-48 47 49 52 24 53 54 26 55 PIN NAME nROM/ nPCMCIA TYPE I/O4 with pullup A0-9 I ** A10/nFWE I O4 A11/nFCS I O4 A12-18 A19/nCE1 AEN/ nREG/ nAS nSBHE/ nCE2 IOCHRDY/ nWAIT I ** I with pullup ** DESCRIPTION This pin is sampled at the end of RESET.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet PIN NO. TQFP QFP 55-58 6057-60, 63 7-10 62-65, 12-15 9-12, 14-17 PIN NAME D0-15 TYPE I/O24 IS with pullup ** IS with pullup ** 65 67 RESET 25 27 BALE/nWE 17 19 INTR0/ nIREQ/ INTR O24 18 20 INTR1/ nINPACK O24 20 22 INTR2 O24 21 23 INTR3 O24 23 25 nIOCS16/ nIOIS16 OD24 49 51 nIORD/ xDS IS with pullup ** DESCRIPTION Bidirectional. 16 bit data bus used to access the LAN91C96 internal registers.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet PIN NO. TQFP QFP 50 52 51 53 PIN NAME nIOWR/ R/nW nMEMR/ nOE TYPE IS with pullup ** IS with pullup ** 5 7 EESK O4 4 2 6 4 O4 O4 3 5 EECS EEDO/ SDOUT EEDI 96,97 98,99 IOS0-1 99 1 IOS2 70 72 nTXLED/ nTXEN 69 69 71 nBSELED/ RXD nRXLED/ RXCLK 68 70 nLNKLED/ TXD 1 3 ENEEP SMSC LAN91C96 5v&3v 68000 – Read/nWrite strobe to read from or write to the chip.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet PIN NO. TQFP QFP 91 93 PIN NAME nEN16 TYPE I with pullup ** 94 96 XTAL1 Iclk ** 95 97 XTAL2 Iclk 83 82 77 76 85 84 79 78 RECP/ RECN TXP/nCOLL TXN/nCRS Diff. Input ** Diff. Output I ** 81 80 83 82 COLP COLN 85 84 87 86 TPERXP TPERXN 75 73 77 75 72 74 66 INTERNAL ENDEC - (nXENDEC pin open). In this mode TXP and TXN are the AUI transmit differential outputs.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet PIN NO. TQFP QFP 100,6, 2,8,18, 24,31, 22,29 56,66, 54,64,92, 16 94 78,86 80,88,89 87 4.1 PIN NAME GND TYPE DESCRIPTION Ground pins. AGND Analog ground pins. Buffer Symbols O4 Output buffer with 2mA source and 4mA sink at 5V. Output buffer with 1mA source and 2mA sink at 3.3V I/O4 Output buffer with 2mA source and 4mA sink at 5V. Output buffer with 1mA source and 2mA sink at 3.3V.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet DATABU ADDRES BUS ARBITE ENDE CSMA/C AUI BUS INTERFAC CONTROL MMU TWISTED TRANSCEIVE 10BASE- RAM Figure 4.1 - LAN91C96 Internal Block Diagram Revision 1.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet Chapter 5 Functional Description Except for the bus interface, the functional behavior of the LAN91C96 after initial configuration is identical for LOCAL BUS and PCMCIA modes. The LAN91C96 includes an arbitrated shared memory of 6144 bytes. Any portion of this memory can be used for receive or transmit packets. The MMU unit allocates RAM memory to be used for transmit and receive packets, using 256 byte pages.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet The LAN91C96 consists of an integrated Ethernet controller mapped entirely in I/O space. In addition, PCMCIA attribute memory space is decoded to interface an external CIS ROM, with configuration registers as per PCMCIA 3.X extensions (except COR) implemented on-chip in attribute space above the ROM decode area. The PCMCIA Configuration Registers are accessible in I/O space and also to allow non-PCMCIA dual function designs.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet 1536 RX AREA 1536 TX AREA RCV VS. TX AREA SELECTION 11-BIT LOGICAL ADDRESS POINTER REGISTER RCV BIT MMU RX PACKET NUMBER MMU TX PACKET NUMBER PHYSICAL MEMORY PAGE = 256 bytes Datasheet Figure 5.1 – Mapping and Paging vs. Receive and Transmit Area SMSC LAN91C96 5v&3v Page 25 DATASHEET Revision 1.
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Revision 1.0 (10-24-08) Page 26 DATASHEET TX FIFO TX COMPLETION FIFO FIFO PORTS REGISTER CPU SIDE PACKET NUMBER REGISTER PACKET #C DATA COUNT STATUS DATA COUNT STATUS DATA LINEAR ADDRESS TO CSMA PACKET #B PACKET #A COUNT STATUS MMU MAPPING C B C A B MEMORY Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet Figure 5.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet LINEAR ADDRESS FROM CSMA SIDE CPU FIFO PORTS REGISTER RX FIFO PACKET #E DATA COUNT STATUS PACKET #D DATA COUNT STATUS MMU MAPPING E D E D MEMORY Datasheet Figure 5.3 – Receive Queues and Mapping SMSC LAN91C96 5v&3v Page 27 DATASHEET Revision 1.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet EEPROM INTERFACE Control Control Control Control Address 8-16 bit Bus Interface Unit Control ENDEC Control AUI Arbiter MMU TX/RX FIFO Pointer Ethernet Protocol Handler DMA (EPH) TPO TX Data WR FIFO TX Data 6K Byte SRAM Data RD FIFO Twisted Pair Transceiver TPI RX Data RX Data Figure 5.4 - LAN91C96 Internal Block Diagram with Data Path Revision 1.
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SMSC LAN91C96 5v&3v Page 29 DATASHEET DATA REGISTER (FIFOS) POINTER REGISTER READ REG READ DATA PACKET # RX FIFO PACKET NUMBER DATA RAM ADDRESS PHYSICAL ADDRESS MMU LOGICAL ADDRESS CPU/nLAN (FROM ARBITER) RCV TX (PACKET NUMBER REG) POINTER REGISTER & COUNTER WRITE DATA WRITE REG LATCH READ POINTER INC LOAD TX COMPLETION FIFO TX FIFO PNR DMA DATA ADDRESS T/nR PACKET # RX FIFO CSMA/CD Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet Figure 5.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet Table 5.1 - LAN91C96 Address Space SIGNALS USED nOE, nWE LOCAL BUS N PCMCIA Configuration Registers nOE, nWE Ethernet I/O space nIORD/ nIOWR (68K: xDS, R/nW) PCMCIA Attribute Memory (Note 5.1) Note 5.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet Table 5.3 - Bus Transactions In PCMCIA Mode 8 BIT MODE A0 0 NCE1 0 NCE2 X D0-7 Even byte 1 X 0 0 1 0 X X 0 Odd byte 0 1 X X 0 0 1 1 1 1 0 1 D8-15 - ((IOis8=1) + (nEN16=1). (16BIT=0)) 16 BIT MODE NO CYCLE Even byte Odd byte Even byte Odd byte - - otherwise Odd byte NO CYCLE Table 5.4 - Bus Transactions In 68000 Mode D0-7 D8-15 ILLEGAL ACCESS Even byte Odd byte 8 BIT MODE 16 BIT MODE (A0=0).(nSBHE=0) 5.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet Table 5.5 - Interrupt Merging FUNCTION Interrupt Output Ethernet Interrupt Source Ethernet Interrupt Enable Ethernet Interrupt Status Bit 5.3 PCMCIA MODE LOCAL BUS MODE INTR0-3 nIREQ when function is Ready. Acts as ready line at power up. I.e.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet 5.5 LAN91C96 Power Down States Table 5.6 - LOCAL BUS Mode Defined States (Refer To Table 5.7 For Next States To Wake-Up Events) CURRENT STATE NO.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet ECSR Power Down bit must not be set to one (1) in LOCAL BUS mode. Table 5.8 - PCMCIA Mode (Refer To Table 5.7 For Next States To Wake-Up Events) CURRENT STATE NO.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet NEXT STATE ECSR CTR PWR PWRDWN DOWN BIT 0 0 NO.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet PCMCIA Configuration Registers Address 8000-8003h The PCMCIA Configuration Registers are stored inside the LAN91C96 above the external Attribute Memory address space. These registers are used to configure and control the PCMCIA related functionality of the Ethernet. These registers are eight bit wide and reside on even locations. The LAN91C96 will ignore odd access to this area and ignore writes.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet register are not accessible) is allowed. IREQ is not generated for this function and INPACK* is not returned for accesses to the Ethernet registers. Note: Magic packet bit setting is ignored if the function is disabled.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet Chapter 6 Frame Format in Buffer Memory for Ethernet The frame format in memory is similar to that in the TRANSMIT and RECEIVE areas. The first word is reserved for the status word, the next word is used to specify the total number of bytes, and that in turn is followed by the data area. The data area holds the packet itself, and its length is determined by the byte count. The frame memory format is word oriented.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet relevant. The transmit byte count least significant bit will be assumed 0 by the controller regardless of the value written in memory. The maximum size of the frame can be stored in 6 pages (256 bytes per page), the maximum BYTE COUNT number is 1536. DATA AREA (in RAM) The data area starts at offset 4 of the packet structure, and it can extend for up to 1531 bytes.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet ODDFRM - This bit when set indicates that the received frame had an odd number of bytes. TOOLNG - The received frame is longer than the 802.3 maximum size (1518 bytes on the cable). TOOSHORT - The received frame is shorter than the 802.3 minimum size (64 bytes on the cable). HASH VALUE - Provides the hash value used to index the Multicast Registers. Can be used by receive routines to speed up the group address search.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet Figure 6.2 - LAN91C96 Registers SMSC LAN91C96 5v&3v Page 41 DATASHEET Revision 1.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet Chapter 7 Registers Map in I/O Space 7.1 I/O Space Access The address is determined by the Ethernet I/O Base Registers. The Ethernet I/O space can be configured as an 8 or 16 bit I/O space, and is similar to the LAN91C94, LAN91C92, etc. I/O space mapping. To limit the I/O space requirements to 16 locations, the registers are Split into 4 banks in LOCAL BUS mode and 5 banks in PCMCIA mode.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet BANK SELECT REGISTER OFFSET NAME BANK SELECT REGISTER # in HEX TYPE SYMBOL READ/WRITE BSR 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BS2 BS1 BS0 0 0 0 X X X X X BS2, BS1, BS0 - Determine the bank presently in use. This register is always accessible except in power down mode and is used to select the register bank in use.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet NOCRC - Does not append CRC to transmitted frames when set, allows software to insert the desired CRC. Defaults to zero, namely CRC inserted. FDSE - Full Duplex Switched Ethernet. When set, the LAN91C96 is configured for Full Duplex Switched Ethernet, it defaults clear to normal CSMA/CD protocol.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet Table 7.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet WAKEUP - When this bit is set, it indicates that a receive packet was received that had the “Magic” packet (MP) signature of the node’s own Individual address repetitions in it. This bit indicates a valid detection for magic packet. TX_DEFR - Transmit Deferred. When set, carrier was detected during the first 6.4 uSec of the inter frame gap. Cleared at the end of every packet sent. LTX_BRD - Last transmit frame was a broadcast.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet FILT_CAR - Filter Carrier. When set filters leading edge of carrier sense for 12 bit times. Otherwise recognizes a receive frame as soon as carrier sense is active. STRIP_CRC - When set it strips the CRC on received frames. When clear the CRC is stored in memory following the packet. Defaults low. RXEN - Enables the receiver when set. If cleared, completes receiving current frame and then goes idle. Defaults low on reset.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet I/O SPACE - BANK0 OFFSET 8 NAME MEMORY INFORMATION REGISTER TYPE READ ONLY SYMBOL MIR For software compatibility with other LAN9000 parts all memory-related information is represented in 256 x M byte units, where the multiplier M is determined by the MCR upper byte. M equals “1” for the LAN91C96.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet Note 7.1 DEVICE FEAST BIT 11 0 BIT 10 1 BIT 9 0 M 2 LAN91C90 0 0 1 1 FUTURE FUTURE FUTURE 0 1 1 1 0 0 1 0 1 4 8 16 MAX MEMORY SIZE 256 (Note 7.1) 256 (Note 7.1) 2=128k 256 (Note 7.1) 256 (Note 7.1) 1=64k 256k 512k 1M Bits 11, 10 and 9 are read only bits used by the software driver to transparently run on different controllers of the LAN9000 family.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet INT SEL1-0 - In LOCAL BUS mode, used to select one out of four interrupt pins. The three unused interrupts are tristated. INT SEL1 INT SEL0 INTERRUPT PIN USED 0 0 INTR0 0 1 INTR1 1 0 INTR2 1 1 INTR3 I/O SPACE - BANK1 OFFSET 2 NAME BASE ADDRESS REGISTER TYPE READ/WRITE SYMBOL BAR For LOCAL BUS mode only, this register holds the I/O address decode option chosen for the I/O and ROM space.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet I/O SPACE - BANK1 OFFSET 4 THROUGH 9 NAME INDIVIDUAL ADDRESS REGISTERS TYPE READ/WRITE SYMBOL IAR These registers are loaded starting at word location 20h of the EEPROM upon hardware reset or EEPROM reload. The registers can be modified by the software driver, but a STORE operation will not modify the EEPROM Individual Address contents.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet I/O SPACE - BANK1 OFFSET A NAME GENERAL ADDRESS REGISTERS 0 0 0 0 TYPE READ/WRITE SYMBOL GPR 0 HIGH DATA BYTE 0 0 0 0 0 0 LOW DATA BYTE 0 0 0 0 0 This register can be used as a way of storing and retrieving non-volatile information in the EEPROM to be used by the software driver.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet AUTO RELEASE - When set, transmit pages are released by transmit completion if the transmission was successful (when TX_SUC is set). In that case there is no status word associated with its packet number, and successful packet numbers are not even written into the TX COMPLETION FIFO.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet I/O SPACE - BANK2 OFFSET NAME 0 MMU COMMAND REGISTER TYPE WRITE ONLY BUSY bit readable SYMBOL MMUCR This register is used by the CPU to control the memory allocation, de-allocation, TX FIFO and RX FIFO control.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet Can be used following 6 (to release receive packet memory in a more flexible way than 8). 1100 C) ENQUEUE PACKET NUMBER INTO TX FIFO - This is the normal method of transmitting a packet just loaded into RAM. The packet number to be enqueued is taken from the PACKET NUMBER REGISTER. 1110 F) RESET TX FIFOs - This command will reset both TX FIFOs.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet I/O SPACE - BANK2 OFFSET 3 FAILED 1 NAME ALLOCATION RESULT REGISTER 0 0 0 TYPE READ ONLY ALLOCATED PACKET NUMBER 0 0 0 SYMBOL ARR 0 FAILED - A ”0” indicates a successful allocation completion. If the allocation fails the bit is set and only cleared when the pending allocation is satisfied. Defaults high upon reset and reset MMU command.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet I/O SPACE - BANK2 OFFSET 6 NAME POINTER REGISTER RCV AUTO INCR. READ 0 0 0 0 0 0 Reserved TYPE READ/WRITE Reserved 0 0 POINTER LOW 0 0 SYMBOL PTR POINTER HIGH 0 0 0 0 0 0 POINTER REGISTER - The value of this register determines the address to be accessed within the transmit or receive areas. It will auto-increment on accesses to the data register when AUTO INCR. is set.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet This register is mapped into two uni-directional FIFOs that allow moving words to and from the LAN91C96 regardless of whether the pointer address is even or odd. Data goes through the write FIFO into memory, and is pre-fetched from memory into the read FIFO. If byte accesses are used, the appropriate (next) byte can be accessed through the Data Low or Data High registers. The order to and from the FIFO is preserved.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet Flow of events for an insertion of a transmit packet: 1. Disable the Transmitter 2. Remove and release any “transmit done” packets in the TX FIFO 3. Via polling or an interrupt driven event, determine status of TX IDLE INT bit and wait until this bit is set. This will determine when the transmitter is truly done with all transmit events. 4. Remove and store (if any, in software) Packet numbers from the transmit FIFO.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet TX EMPTY INT - Set if the TX FIFO goes empty, can be used to generate a single interrupt at the end of a sequence of packets enqueued for transmission. This bit latches the empty condition, and the bit will stay set until it is specifically cleared by writing the acknowledge register with the TX EMPTY INT bit set. If a real time reading of the FIFO empty is desired, the bit should be first cleared and then read.
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SMSC LAN91C96 5v&3v Page 61 DATASHEET SQET LOST CARR LATCOL 16COL TE_Enable CR_Enable CTR-ROL LE_Enable Fatal TX Error Edge Detector on Link Err nWRACK IntAck7 IntAck4 IntAck2 IntAck1 nRDIST nQ D S Q MDINT nQ D S Q RX_OVRN ALLOCATION FAILED nQ D S Q TX FIFO EMPTY nQ D S Q TX FIFO NOT EMPTY 6 5 4 3 2 1 0 DATA BUS D[15:0] OE D[7:0] Interrupt Status Register 7 RCV FIFO NOT EMPTY 7 6 5 4 3 2 1 0 nOE D[15:8] Interrupt Mask Register MAIN INTERRUPTS MDINT EPH IN
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet I/O SPACE - BANK 3 OFFSET 0 THROUGH 7 0 NAME MULTICAST TABLE 0 TYPE READ/WRITE SYMBOL MT 0 Multicast Table 0 0 0 0 0 0 0 0 0 0 0 0 Multicast Table 1 0 0 0 0 0 Multicast Table 2 0 0 0 0 0 0 0 0 0 0 0 Multicast Table 3 0 0 0 0 0 Multicast Table 4 0 0 0 0 0 0 Multicast Table 5 0 0 0 0 0 0 Multicast Table 6 0 0 0 0 0 0 Multicast Table 7 0 0 0 0 0 0 0 0 0 0 0 The 64 bit multi
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet nXNDEC - Read only bit reflecting the status of the nXENDEC pin. IOS0-2 - Read only bits reflecting the status of the IOS0-2 pins. MDO - The value of this bit drives the EEDO pin when MDOE=1. MDCLK - The value of this bit drives the EESK pin when MDOE=1. MDOE - When this bit is high pins EEDO EECS and EESK will be used for transceiver management functions, otherwise the pins assume the EEPROM values.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet I/O SPACE - BANK3 OFFSET C 0 RCV DISCRD 0 NAME RCV REGISTER 0 1 0 0 TYPE READ/WRITE RCV COUNTER 1 0 MBO MBO 1 1 SYMBOL RCV 0 MBO 1 MBO 1 MBO 1 1 1 RCV DISCRD - Set to discard a packet being received. MBO – Must be 1. Rcv Counter - This 8 bit value is the “Real Time” count, in bytes, of the current Receive packet (this includes the 4 bytes of status and packet length).
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet Chapter 8 Theory of Operation The concept of presenting the shared RAM as a FIFO of packets, with a memory management unit allocating memory on a per packet basis responds to the following needs: Memory allocation for receive vs. transmit - A fixed partition between receive and transmit area would not be efficient.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet B) No collision detection - There are no collisions in a switched full duplex environment. MAGIC PACKET SUPPORT If the WAKEUP_EN bit in the Control Register (Bank1, Offset C) is set, the controller will generate the interrupt If this bit is not set, this functionality is disabled. Setting (1) the bit is meaningful only if the function is enabled.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet 8.1 Typical Flow of Events for Transmit (Auto Release = 0) S/W DRIVER MAC SIDE 1 ISSUE ALLOCATE MEMORY FOR TX - N BYTES - the MMU attempts to allocate N bytes of RAM. 2 WAIT FOR SUCCESSFUL COMPLETION CODE - Poll until the ALLOC INT bit is set or enable its mask bit and wait for the interrupt. The TX packet number is now at the Allocation Result Register.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet 7 a) SERVICE INTERRUPT - Read Interrupt Status Register. If it is a transmit interrupt, read the TX FIFO Packet Number from the FIFO Ports Register. Write the packet number into the Packet Number Register. The corresponding status word is now readable from memory. If status word shows successful transmission, issue RELEASE packet number command to free up the memory used by this packet.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet 7 8 a) SERVICE INTERRUPT – Read Interrupt Status Register, exit the interrupt service routine. b) Option 1) Release the packet. a) The MAC generates a TXEMPTY interrupt upon a completion of a sequence of enqueued packets. b) If a TX failure occurs on any packets, TX INT is generated and TXENA is cleared, transmission sequence stops. The packet number of the failure packet is presented at the TX FIFO PORTS Register.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet ISR Save Bank Selec & Address Ptr Registerst Mask Interrupts Read Interrupt Register No Yes TX INTR? Call TX INTR or TXEMPTY INTR RX INTR? Yes No Call RXINTR Get Next TX No Yes No Packet Available for Transmission? ALLOC INTR? Yes Write Allocated Pkt# into Packet Number Reg. Call ALLOCATE Write Ad Ptr Reg.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet RX INTR Write Ad. Ptr. Reg. & Read Word 0 from RAM Yes Destination Multicast? No Read Words 2, 3, 4 from RAM for Address Filtering No Address Filtering Pass? Yes No Status Word OK? Yes Do Receive Lookahead Get Copy Specs from Upper Layer No Okay to Copy? Yes Copy Data Per Upper Layer Specs Issue "Remove and Release" Command Return to ISR Figure 8.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet TX Interrupt With AUTO_RELEASE = FALSE 1. Save the Packet Number Register Saved_PNR = Read Byte (Bank 2, Offset 2) 2. Read the EPH Status Register Temp = Read (Bank 0, Offset 2) 3. Acknowledge TX Interrupt Write Byte (0x02, (Bank 2, Offset C)); 4. Check for Status of Transmission If ( Temp AND 0x0001) { //If Successful Transmission Step 4.1.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet TXEMPTY INTR Write Acknowledge Reg. with TXEMPTY Bit Set Read TXEMPTY & TX INTR TXEMPTY = 0 & TXINT = 0 (Waiting for Completion) TXEMPTY = X & TXINT = 1 (Transmission Failed) TXEMPTY = 1 & TXINT = 0 (Everything went through successfully) Read Pkt.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet DRIVER SEND ALLOCATE Choose Bank Select Register 2 Issue "Allocate Memory" Command to MMU Call ALLOCATE Read Interrupt Status Register Exit Driver Send Yes Allocation Passed? No Read Allocation Result Register Write Allocated Packet into Packet # Register Store Data Buffer Pointer Write Address Pointer Register Clear "Ready for Packet" Flag Copy Part of TX Data Packet into RAM Enable Allocation Interrupt Write S
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet MEMORY PARTITIONING Unlike other controllers, the LAN91C96 does not require a fixed memory partitioning between transmit and receive resources. The MMU allocates and de-allocates memory upon different events. An additional mechanism allows the CPU to prevent the receive process from starving the transmit memory allocation.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet 1. One interrupt per packet: enable TX INT, set AUTO RELEASE=0. The software driver can find the completion result in memory and process the interrupt one packet at a time. Depending on the completion code the driver will take different actions. Note that the transmit process is working in parallel and other transmissions might be taking place. The LAN91C96 is virtually queuing the packet numbers and their status words.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet NXENDEC PIN 0 1 1 PWRDN PIN X 0 1 PWRDN BIT 0 0 0 X X 1 SMSC LAN91C96 5v&3v Normal external ENDEC operation Normal internal ENDEC operation Powerdown - Normal mode restored by PWRDWN pin going low Powerdown - Bit is cleared by a write access to any LAN91C96 register or by hardware reset Page 77 DATASHEET Revision 1.
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Revision 1.0 (10-24-08) OPTIONS TWO INTERRUPT INT ALLOC INT TX TX EMPTY INT INT RCV STATUS REGISTER M.S. BIT ONLY PACKET NUMBER TX DONE TX COMPLETION FIFO 'NOT EMPTY' 'EMPTY' TX FIFO Page 78 DATASHEET PACK # OUT CPU ADDRESS REGISTER PACKET NUMBER PACKET # RAM PHYSICAL ADDRESS MMU LOGICAL ADDRESS RX FIFO NUMBER RX PACKET RX FIFO PACKET NUMBER CSMA ADDRESS 'NOT EMPTY' CSMA/CD Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet Figure 8.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet Chapter 9 Functional Description of the Blocks 9.1 Memory Management Unit The MMU interfaces the on-chip RAM on one side and the arbiter on the other for address and data flow purposes. For allocation and de-allocation, it interfaces the arbiter only. The MMU deals with a single ported memory and is not aware of the fact that there are two entities requesting allocation and actually accessing memory.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet The data path routed by the arbiter goes between memory (the data path does not go through the MMU) on one side and either the CPU side bus or the data path of the CSMA/CD core. The data path between memory and the Data Register is in fact buffered by a small FIFO in each direction. The FIFOs beneath the Data Register can be read and written as bytes or words, in any sequential combination.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet If the access time is the problem, IOCHRDY should be negated for all accesses to the LAN91C96. This can be achieved by programming the NO WAIT ST bit in the configuration register to “0”. The LAN91C96 will negate IOCHRDY for 100ns to 150ns on every access to any register. If the cycle time is the problem, programming NO WAIT ST as described before will solve it but at the expense of slowing down all accesses.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet 9.6 DMA Block The DMA block resides between the CSMA/CD block and the arbiter. It can interface both the data path and the control path of the CSMA/CD block for different operations. Its functions include the following: Start transmission process into the CSMA/CD block. Generate CSMA/CD side addresses for accessing memory during transmit and receive operations. Generate MMU memory requests and verify success.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet DMA block when the CSMA/CD block is ready to proceed on to the next transmission. By reading the TX EMPTY INT bit the CPU can determine if this FIFO is empty. The transmit completion FIFO stores the packet numbers that were already transmitted but not yet acknowledged by the CPU. The CPU can read the next packet number in this FIFO from the FIFO Ports Register.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet RAM PACK # OUT ALLOCATION RESULT REGISTER MMU RELEASE REGISTER MMU COMMAND DECODER CPU ADDRESS ALLOCATE LOGICAL ADDRESS TX DONE PACKET NUMBER INT TX FIFO COMPLETION TX FIFO WR REGISTER PACKET NUMBER PACK # OUT PHYSICAL ADDRESS DMA RELEASE PACKET # ALLOCATE CSMA ADDRESS RX PACKET NUMBER RD RX FIFO PACKET NUMBER RX FIFO CSMA/CD Datasheet FIGURE 9.1 - MMU PACKET NUMBER FLOW AND RELEVANT REGISTERS 9.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet For receive, the CPU sets RXEN as a way of starting the CSMA/CD block receive process. The CSMA/CD block will send data after address filtering through the data path to the DMA block. Data is transferred into memory as it is received, and the final check on data acceptance is the CRC checking done by the CSMA/CD block.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet 9.10 10Base-T The 10BASE-T interface conforms to the twisted pair MAU addendum to the 802.3 specification. On the transmission side, it converts the NRZ data from the controller to Manchester data and provides the appropriate signal level for driving the media. Signal are predistorted before transmission to minimize ISI.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet 9.13.3 Jabber Function This integrated function prevents the DTE from locking into a continuous transmit state. In 10BASE-T mode, if transmission continues beyond the specified time limit, the jabber function inhibits further transmission and asserts the collision indicator nCOLL. The limits for jabber transmission are 20 to 15 ms in 10BASE-T mode. In the AUI mode, the jabber function is performed by the external transceiver.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet 9.14.5 Collision Detection Function In the 10BASE-T mode, a collision state is indicated when there are simultaneous transmissions and receptions on the twisted pair link. During a collision state, the nCOLL signal is asserted. If the received data ends and the transmit control signal is still active, the transmit data is sent to the MAC within 9 bit times.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet Chapter 10 Board Setup Information Configuration Register EEPROM WORD ADDRESS IOS Value * 4 Base Register (IOS Value *4) + 1 REGISTER The following parameters are obtained from the EEPROM as board setup information: ETHERNET INDIVIDUAL ADDRESS I/O BASE ADDRESS ROM BASE ADDRESS 8/16 BIT ADAPTER 10BASE-T or AUI INTERFACE INTERRUPT LINE SELECTION All the above mentioned values are read from the EEPROM
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet On EEPROM write operations (after setting the STORE bit) the value of the GENERAL PURPOSE REGISTER is written at the EEPROM word address defined by the POINTER REGISTER 6 least significant bits. RELOAD and STORE are set by the user to initiate read and write operations respectively. Polling the value until read low is used to determine completion.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet nAS to nAEN/nAS 68000 Address<23:1> to 91C96 Address Bus DATA to DATA (Upper and lower bytes swapped) Interrupt (if used) to INT0 The following signals MUST be pulled as stated: LAN91C96 Address bit 0 tied low LAN91C96 nSBHE input tied low All INTx must have a 1KΩ to 10KΩ pull-up to keep the line high while the drivers are tri-stated. 16 BITS IOS2-0 W OR D AD DRESS 000 0h CONFIGURATION REG.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet Chapter 11 Operational Description 11.1 Maximum Guaranteed Ratings* Operating Temperature Range ...................................................................................................0°C to 70°C Storage Temperature Range ...............................................................................................-55°C to +150°C Lead Temperature Range (soldering, 10 seconds) .......................................
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet PARAMETER ICLK Input Buffer SYMBOL Low Input Level VILCK High Input Level VIHCK MIN TYP MAX UNITS 0.4 V COMMENTS V 3.3 Input Voltage Levels for Vcc = 3.3V (Revisions E and later) I Type Input Buffer 0.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet PARAMETER ID Type Buffers Input Current SYMBOL MIN IIH TYP MAX UNITS COMMENTS +50 +150 μA VIN = VCC μA VIN = 0 +100 μA VIN = VCC 0.4 V IOL = 4 mA V IOH = -2 mA +10 μA VIN = 0 to VCC 0.5 V IOL = 24 mA V IOH = -12 mA +10 μA VIN = 0 to VCC 0.5 V IOL = 24 mA V IOH = -12 mA +10 μA VIN = 0 to VCC 0.4 V IOL = 4 mA V IOH = -2 mA Input Current for Vcc = 3.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet PARAMETER O162 Type Buffer SYMBOL MIN Low Output Level VOL High Output Level VOH 2.4 Output Leakage ILEAK -10 TYP MAX UNITS COMMENTS 0.5 V IOL = 16 mA V IOH = -2 mA +10 μA VIN = 0 to VCC 0.5 V IOL = 24 mA +10 μA VIN = 0 to VCC 0.4 V IOL = 2 mA V IOH = -1 mA +10 μA VIN = 0 to VCC 0.5 V IOL = 16 mA V IOH = -6 mA +10 μA VIN = 0 to VCC 0.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet PARAMETER O162 Type Buffer SYMBOL MIN Low Output Level VOL High Output Level VOH 2.4 Output Leakage ILEAK -10 TYP MAX UNITS COMMENTS 0.5 V IOL = 8 mA V IOH = -1 mA +10 μA VIN = 0 to VCC 0.5 V IOL = 12 mA +10 μA VIN = 0 to VCC 95 mA All outputs open. OD24 Type Buffer Low Output Level VOL Output Leakage ILEAK Supply Current for Vcc = 5.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet VCC = 5V +/- 10% PARAMETER MIN 10BASE-T Receiver Threshold Voltage Receiver Squelch Receiver Common Mode Range Transmitter Output: Voltage Source Resistance Transmitter Output DC Offset Transmitter Backswing Voltage to Idle Differential Input Voltage Receiver Threshold Voltage Receiver Squelch Receiver Common Mode Range Transmitter Output Voltage (R=78Ω) Transmitter Backswing Voltage to Idle Input Differential Voltage Output
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet VCC = 3.3V +/- 10% for Revisions E and later PARAMETER MIN 10BASE-T Receiver Threshold Voltage Receiver Squelch Receiver Common Mode Range Transmitter Output: Voltage Source Resistance Transmitter Output DC Offset Transmitter Backswing Voltage to Idle Differential Input Voltage 225 0 +/- 1.3 TYP TBD 260 +/- 1.5 +/- 0.520 AUI Receiver Threshold Voltage Receiver Squelch Receiver Common Mode Range 120 0 +/- 0.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet Chapter 12 Timing Diagrams t63 t60 A0-9,A15 t62 t61 valid valid t63 t60 nREG nCE1 nWE t64 t57 nOE t59 t65 t58 D0-7 t57 t58 t59 t60 t61 t62 t63 t64 t65 valid valid Parameter min Write Data Setup to nWE Rising Write Data Hold after nWE Rising nOE Low to Valid Data Address, nREG Setup to nWE Active Address, nREG Hold after nOE Inactive Address, nREG Setup to nOE Active Address, nREG Hold after Control Inactive nC
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet A0-15 AEN, nSBHE VALID ADDRESS VALID ADDRESS t4 t15 nIOCS16 t20 t3 nIORD t6 t5 VALID DATA OUT D0-15 Z Parameter t3 t4 t5 t6 t15 t20 VALID DATA OUT min Address, nSBHE, AEN Setup to Control Active Address, nSBHE, AEN Hold after Control Inactive nIORD Low to Valid Data nIORD High to Data Floating A4-A15, AEN Low, BALE High to nIOCS16 Low Cycle time* typ max 10 20 185 Z units ns ns 25 ns 15 12 ns ns ns BALE
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet t51 A0-9,A15 t52 valid t49 t47 nREG t48 t50 nCE1,nCE2 t20 nIORD t53 D0-15 valid t46 t46 nINPACK Parameter t46 t47 t48 t20 t49 t50 t51 t52 t53 min nIORD to INPACK Delay nREG Low to Control Active nCE1,nCE2 Setup to Control Active Cycle Time (No Wait States) nREG Hold after Control Active nCE1,nCE2 Hold after Control Inactive Address Setup to Control Active Address Hold after Control Inactive nIORD Active to Data Valid
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet A0-15 AEN, nSBHE VALID ADDRESS VALID ADDRESS t4 t15 nIOCS16 t3 t20 nIOWR t7 D0-15 t8 Parameter t3 t4 t7 t8 t15 t20 VALID DATA VALID DATA IN min Address, nSBHE, AEN Setup to Control Active Address, nSBHE, AEN Hold after Control Inactive Data Setup to nIOWR Rising Data Hold after nIOWR Rising A4-A15, AEN Low, BALE High to nIOCS16 Low Cycle time* typ max units 10 5 ns ns 5 5 ns ns ns 12 185 ns BALE Tied High
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet t51 A0-9,A15 nREG t52 valid t47 t49 t48 t50 nCE1,nCE2 t20 t54 t55 nIOWR D0-15 valid Parameter t47 t48 t49 t50 t51 t52 t20 t54 t55 min nREG Low Setup to Control Active nCE1,nCE2 Setup to Control Active nREG Hold after Control Inactive nCE1,nCE2 Hold after Control Inactive Address Setup to Control Active Address Hold after Control Inactive Cycle Time (No Wait States) Write Data Setup to nIOWR Rising Write Data Hold a
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet A0-15 AEN, nSBHE VALID ADDRESS VALID ADDRESS nIOCS16 t20 nIORD nIOWR t9 Z Z t10 IOCHRDY D0-D15 Z VALID DATA Parameter t9 t10 t20 Z VALID DATA min Control Active to IOCHRDY Low IOCHRDY Low Pulse Width* Cycle time** 100 185 typ max units 12 150 ns ns ns Z *Note: Assuming NO WAIT ST = 0 in configuration register and cycle time observed.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet A0-15 (ISA) AEN, nSBHE VALID ADDRESS nIOCS16 nIORD t9 Z IOCHRDY t18 Z t19 VALID DATA OUT D0-D15 Parameter t9 t18 t19 min typ Control Active to IOCHRDY Low IOCHRDY Width when Data is Unavailable at Data Register Valid Data to IOCHRDY Inactive max units 15 ns 575 225 ns ns IOCHRDY is used instead of meeting t20 and t43. "No Wait St' bit is 1 - IOCHRDY only negated if needed and only for Data Register access.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet A0-15 (ISA) AEN, nSBHE VALID ADDRESS nIOCS16 nIOWR t9 IOCHRDY t18 Z D0-D15 VALID DATA IN Parameter t9 t18 Z min typ Control Active to IOCHRDY Low IOCHRDY Width when Data Register is Full max units 15 425 ns ns IOCHRDY is used instead of meeting t20 and t44. 'No Wait St' bit is 1 - IOCHRDY only negated if needed and only for Data Register access. Figure 12.8 – Data Register Special Write Access Revision 1.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet A0-15 (ISA) AEN VALID ADDRESS VALID ADDRESS t3 nIOWR t3 nIORD t7 t8 t5 Z D0-7 Parameter t3 t5 t7 t8 Z VALID DATA OUT min Address, nSBHE, AEN Setup to Control Active nIORD Low to Valid Data Data Setup to nIOWR Rising Data Hold after nIOWR Rising VALID DATA IN typ max 25 40 30 9 units ns ns ns ns Figure 12.9 - 8-Bit Mode Register Cycles SMSC LAN91C96 5v&3v Page 107 DATASHEET Revision 1.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet t3 t10 t2 nAS(nAEN) t4 ADD t5 t6 xDS,LDS,UDS (nIORD) t1 R/nW(nIOWR) t7 t9 DATA Figure 12.10 - 68000 Read Timing t1 t2 t3 t4 t5 t6 t7 t9 t10 Revision 1.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet t3 t10 t2 nAS (nAEN) t4 ADD t6 t5 t7 xDS,LDS,UDS (nIORD) t1 R/nW (nIOWR) t9 t8 DATA Figure 12.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet A0-19 ADDRESS VALID t3 t4 nMEMRD Z D0-15 t16 t17 nROM Parameter min typ max units t3 Address Setup to Control Active 10 ns t4 Address Hold after Control Inactive 20 ns t16 nMEMRD Low to nROM Low(Internal) 0 20 ns t17 nMEMRD High to nROM High(Internal) 0 35 ns BALE tied high Figure 12.12 – External ROM Read Access Revision 1.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet t4 AEN A0-15, nSBHE VALID t1 BALE t2 t15 nIOCS16 nIORD nIOWR t1 t2 t3 t4 t15 t5 t3 t5 Parameter min Address, nSBHE Setup to BALE Falling Address, nSBHE Hold after BALE Falling Address, nSBHE, AEN Setup to Control Active AEN Hold after Control Inactive A4-A15, AEN Low, BALE High to nIOCS16 Low BALE Pulse Width 10 5 25 20 typ max units 12 15 ns ns ns ns ns ns t4 not needed. nIOCS16 not relevant in 8-bit mode.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet A0-19 VALID t1 t2 BALE t3 nMEMRD t16 t17 nROM Parameter t1 t2 t3 t16 t17 mi n Address Setup to BALE Falling Address Hold after BALE Falling Address Setup to Control Active nMEMRD Low to nROM Low nMEMRD High to nROM High ty p max 10 5 25 20 35 unit s ns ns ns ns ns Figure 12.14 – External ROM Read Access Using Bale Revision 1.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet EESK EEDO t68 EEDI EECS t21 Parameter t21 EESK Falling to EECS Changing t68 EESK Falling to EEDO Changing min 0 typ max units 15 ns 25 ns 9346 is typically the serial EEPROM used. Figure 12.15 - EEPROM Read SMSC LAN91C96 5v&3v Page 113 DATASHEET Revision 1.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet EESK EEDO t70 EEDI EECS t69 Parameter min typ max units t69 EESK Falling to EECS Changing 5 ns t70 EESK Falling to EEDO Changing 20 ns 9346 is typically the serial EEPROM used. Figure 12.16 - EEPROM Write Revision 1.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet A0-9,A15 valid valid nREG nCE1 t67 t67 t67 t67 t67 t67 t67 t67 t67 t67 t67 t67 nFCS nWE t66 nFWE t66 nOE Parameter t66 t67 min typ max units 20 25 ns ns 0 0 nWE to nFWE Delay Address, nREG, nCE1 Delay to nFCS Figure 12.17 - PCMCIA Attribute Memory Read/Write (A15=0) nTXEN TXD TXCLK t22 t22 t22 Parameter min TXD, nTXEN Delay from TXCLK Falling 0 typ max u unit 25 ns Figure 12.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet t23 t24 RXD RXCLK nCRS t23 Parameter t23 t24 min nCRS, RXD Setup to RXCLK Falling nCRS, RXD Hold after RXCLK Falling typ max 10 30 units ns ns Figure 12.19 – External ENDEC Interface – Receive Data (RXD SAMPLED BY FALLING RXCLK) Revision 1.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet TPETXP t31 t31 TPETXN t32 t32 TPETXDN t33 t33 TPETXDP TWISTED PAIR DRIVERS TXP t34 t34 TXN AUI DRIVERS Parameter t31 t32 t33 t34 min TPETXP to TPETXN Skew TPETXP(N) to TPETXDP(N) Delay TPETXDN to TPETXDP Skew TXP to TXN Skew -1 47 -1 -1.5 typ max units +1 53 +1 1.5 ns ns ns ns Figure 12.20 – Differential Output Signal Timing (10BASE-T and AUI) SMSC LAN91C96 5v&3v Page 117 DATASHEET Revision 1.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 RECP RECN t35 first bit decoded nCRS (internal) t36 1 0 1 1 0 1 0 TPERXP(N) t37 nCRS (internal) first bit decoded t38 Parameter t35 t36 t37 t38 Noise Pulse Width Reject (AUI) Carrier Sense Turn On Delay (AUI) Noise Sense Pulse Width Reject (10BASE-T) Carrier Sense Turn On Delay (10BASE-T) min typ max units 15 50 15 450 25 70 25 500 30 100 30 550 ns ns ns ns Figu
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet last bit b a 1/0 TPERXP TPERXN RECP RECN t39 nCRS (internal) Parameter t39 min 200 Receiver Turn Off Delay typ max units 300 ns Figure 12.22 – Receive Timing – End of Frame (AUI and 10BASE-T) SMSC LAN91C96 5v&3v Page 119 DATASHEET Revision 1.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet t40 t41 TPETXP TPETXN last bit b a 1/0 TXP TXN Parameter t40 t41 min Transmit Output High to Idle in Half-Step Mode Transmit Output High before Idle in Half-Step Mode 200 typ max units 800 ns ns Figure 12.23 – Transmit Timing – End of Frame (AUI and 10BASE-T) Revision 1.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet COLLP COLLN t42 t43 COL (internal) Parameter t42 t43 min typ Collision Turn On Delay Collision Turn Off Delay max units 50 350 ns ns Figure 12.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet t1 t2 t2 CLOCK tR tF Figure 12.26 – Input Clock Timing NAME t1 t2 tR, tF DESCRIPTION Clock Cycle Time for 20 MHz Clock High Time/Low Time for 20 MHz Clock Rise Time/Fall Time Xtal1 Startup time (from 1.6v of Vcc rising) Xtal1 Capture Range (Xtal1 frequency variation) Xtal Internal feedback resistor ADDRESS MIN TYP 50 19.7 20/30 5 50 20.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet Figure 12.28 - 100 PIN QFP Package A A1 A2 D D1 E E1 H L L1 e MIN ~ 0.05 2.55 23.65 19.90 17.65 13.90 0.11 0.73 ~ NOMINAL ~ ~ ~ ~ ~ ~ ~ ~ 0.88 1.95 0.65 Basic ~ MAX 3.4 0.5 3.05 24.15 20.10 18.15 14.10 0.23 1.03 ~ REMARKS Overall Package Height Standoff Body Thickness X Span X body Size Y Span Y body Size Lead Frame Thickness Lead Foot Length Lead Length Lead Pitch Lead Foot Angle 0o 7o θ W 0.20 ~ 0.40 Lead Width R1 0.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet Figure 12.29 - 100 PIN TQFP Package MIN NOMINAL MAX REMARKS A ~ ~ 1.20 Overall Package Height A1 0.05 ~ 0.15 Standoff A2 0.95 ~ 1.05 Body Thickness D 15.80 ~ 16.20 X Span D1 13.90 ~ 14.10 X body Size E 15.80 ~ 16.20 Y Span E1 13.90 ~ 14.10 Y body Size H 0.09 ~ 0.20 Lead Frame Thickness L 0.45 0.60 0.75 Lead Foot Length L1 ~ 1.00 ~ Lead Length e 0.50 Basic Lead Pitch 0o ~ 7o Lead Foot Angle θ W 0.17 0.22 0.27 Lead Width R1 0.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet Chapter 13 LAN91C96 Revisions PAGE(S) SECTION/FIGURE/ENTRY 2 ~ 2 92 Ordering Information All Ordering Information DC Electrical Characteristics 65 Theory of Operation (Magic Packet Support section) I/O Space – Bank1 Offset 2 50 124~125 17 58 61 59 67 CORRECTION Fig.12.28100 pin QFP Package; Fig.12.28100 Pin TQFP Package; Chapter 4 Description of Pin Functions IO Space Bank 2 Offset 2 – Interrupt 1 Figure 7.