Datasheet

10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
Revision 1.92 (06-27-11) 84 SMSC LAN91C111 REV C
DATASHEET
9.8 Register 18. Status Output - Structure and Bit Definition
APOLDIS: Auto Polarity
Disable
1 = Auto
Polarity
Correction
Function
Disabled
1 = Auto
Polarity
Correction
Function
Disabled
0 = Normal 0 = Normal
JABDIS: Jabber Disable
Select
1 = Jabber
Disabled RW
1 = Jabber
Disabled
0 = Enabled 0 = Enabled
MREG: Multiple Register
Access Enable
1 = Multiple
Register Access
Enabled
0 = No Multiple
Register Access
0 = No
Multiple
Register
Access
INTMDIO: Interrupt
Scheme Select
1 = Interrupt
Signaled With
MDIO Pulse
During Idle
1 = Interrupt
Signaled
With MDIO
Pulse During
Idle
0 = Interrupt
Not Signaled
On MDIO
0 = Interrupt
Not Signaled
On MDIO
Reserved: Reserved for
Factory Use
INT LNKFAIL LOSSSYNC CWRD SSD ESD RPOL JAB
R R/LT R/LT R/LT R/LT R/LT R/LT R/LT
00 0 000 0 0
SPDDET DPLXDET Reserved Reserved Reserved Reserved Reserved Reserved
R/LT R/LT R R R R R R
10 0 00000