Datasheet

10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
Revision 1.92 (06-27-11) 66 SMSC LAN91C111 REV C
DATASHEET
8.21 Bank 2 - Interrupt Status Registers
This register can be read and written as a word or as two individual bytes.
The Interrupt Mask Register bits enable the appropriate bits when high and disable them when low. A
MASK bit being set will cause a hardware interrupt.
MDINT - Set when the following bits in the PHY MI Register 18 (Serial Port Status Output Register)
change state.
1. LNKFAIL, 2) LOSSSYNC, 3) CWRD, 4) SSD, 5) ESD, 6) PROL, 7) JAB, 8) SPDDET, 9) DPLXDET.
OFFSET NAME TYPE SYMBOL
C
INTERRUPT STATUS
REGISTER READ ONLY IST
MDINT Reserved EPH INT RX_OVRN
INT
ALLOC INT TX EMPTY
INT
TX INT RCV INT
00000100
OFFSET NAME TYPE SYMBOL
C
INTERRUPT
ACKNOWLEDGE
REGISTER WRITE ONLY IST
MDINT Reserved RX_OVRN
INT
TX EMPTY
INT
TX INT
OFFSET NAME TYPE SYMBOL
D
INTERRUPT MASK
REGISTER READ/WRITE MSK
MDINT
MASK
Reserved EPH INT
MASK
RX_OVRN
INT
MASK
ALLOC INT
MASK
TX EMPTY
INT
MASK
TX INT
MASK
RCV INT
MASK
00000000