Datasheet

10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
Revision 1.92 (06-27-11) 46 SMSC LAN91C111 REV C
DATASHEET
8.3 I/O Space
The base I/O space is determined by the IOS0-IOS2 inputs and the EEPROM contents. To limit the
I/O space requirements to 16 locations, the registers are assigned to different banks. The last word of
the I/O area is shared by all banks and can be used to change the bank in use. Registers are
described using the following convention:
FFSET - Defines the address offset within the IOBASE where the register can be accessed at,
provided the bank select has the appropriate value.
The offset specifies the address of the even byte (bits 0-7) or the address of the complete word.
The odd byte can be accessed using address (offset + 1).
Some registers (like the Interrupt Ack., or like Interrupt Mask) are functionally described as two eight
bit registers, in that case the offset of each one is independently specified.
Regardless of the functional description, all registers can be accessed as doublewords, words or bytes.
The default bit values upon hard reset are highlighted below each register.
A special BANK (BANK7) exists to support the addition of external registers.
OFFSET NAME TYPE SYMBOL
HIGH
BYTE
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
XXXXXXXX
LOW
BYTE
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
XXXXXXXX
Table 8.1 Internal I/O Space Mapping
BANK0 BANK1 BANK2 BANK3
0 TCR CONFIG MMU COMMAND MT0-1
2 EPH STATUS BASE PNR MT2-3
4 RCR IA0-1 FIFO PORTS MT4-5
6 COUNTER IA2-3 POINTER MT6-7
8 MIR IA4-5 DATA MGMT
A RPCR GENERAL PURPOSE DATA REVISION
C RESERVED CONTROL INTERRUPT RCV
E BANK BANK BANK BANK